/ {
#address-cells = <1>;
#size-cells = <1>;
compatible = "brcm,bcm7358";
cpus {
#address-cells = <1>;
#size-cells = <0>;
mips-hpt-frequency = <375000000>;
cpu@0 {
compatible = "brcm,bmips3300";
device_type = "cpu";
reg = <0>;
};
};
aliases {
uart0 = &uart0;
};
cpu_intc: interrupt-controller {
#address-cells = <0>;
compatible = "mti,cpu-interrupt-controller";
interrupt-controller;
#interrupt-cells = <1>;
};
clocks {
uart_clk: uart_clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <81000000>;
};
upg_clk: upg_clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <27000000>;
};
};
rdb {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges = <0 0x10000000 0x01000000>;
periph_intc: interrupt-controller@411400 {
compatible = "brcm,bcm7038-l1-intc";
reg = <0x411400 0x30>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&cpu_intc>;
interrupts = <2>;
};
sun_l2_intc: interrupt-controller@403000 {
compatible = "brcm,l2-intc";
reg = <0x403000 0x30>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&periph_intc>;
interrupts = <48>;
};
gisb-arb@400000 {
compatible = "brcm,bcm7400-gisb-arb";
reg = <0x400000 0xdc>;
native-endian;
interrupt-parent = <&sun_l2_intc>;
interrupts = <0>, <2>;
brcm,gisb-arb-master-mask = <0x2f3>;
brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "bsp_0",
"rdc_0", "raaga_0",
"avd_0", "jtag_0";
};
upg_irq0_intc: interrupt-controller@406600 {
compatible = "brcm,bcm7120-l2-intc";
reg = <0x406600 0x8>;
brcm,int-map-mask = <0x44>, <0x7000000>;
brcm,int-fwd-mask = <0x70000>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&periph_intc>;
interrupts = <56>, <54>;
interrupt-names = "upg_main", "upg_bsc";
};
upg_aon_irq0_intc: interrupt-controller@408b80 {
compatible = "brcm,bcm7120-l2-intc";
reg = <0x408b80 0x8>;
brcm,int-map-mask = <0x40>, <0x8000000>, <0x100000>;
brcm,int-fwd-mask = <0>;
brcm,irq-can-wake;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&periph_intc>;
interrupts = <57>, <55>, <59>;
interrupt-names = "upg_main_aon", "upg_bsc_aon",
"upg_spi";
};
sun_top_ctrl: syscon@404000 {
compatible = "brcm,bcm7358-sun-top-ctrl", "syscon";
reg = <0x404000 0x51c>;
native-endian;
};
reboot {
compatible = "brcm,brcmstb-reboot";
syscon = <&sun_top_ctrl 0x304 0x308>;
};
uart0: serial@406800 {
compatible = "ns16550a";
reg = <0x406800 0x20>;
reg-io-width = <0x4>;
reg-shift = <0x2>;
native-endian;
interrupt-parent = <&periph_intc>;
interrupts = <61>;
clocks = <&uart_clk>;
status = "disabled";
};
uart1: serial@406840 {
compatible = "ns16550a";
reg = <0x406840 0x20>;
reg-io-width = <0x4>;
reg-shift = <0x2>;
native-endian;
interrupt-parent = <&periph_intc>;
interrupts = <62>;
clocks = <&uart_clk>;
status = "disabled";
};
uart2: serial@406880 {
compatible = "ns16550a";
reg = <0x406880 0x20>;
reg-io-width = <0x4>;
reg-shift = <0x2>;
native-endian;
interrupt-parent = <&periph_intc>;
interrupts = <63>;
clocks = <&uart_clk>;
status = "disabled";
};
bsca: i2c@406200 {
clock-frequency = <390000>;
compatible = "brcm,brcmstb-i2c";
interrupt-parent = <&upg_irq0_intc>;
reg = <0x406200 0x58>;
interrupts = <24>;
interrupt-names = "upg_bsca";
status = "disabled";
};
bscb: i2c@406280 {
clock-frequency = <390000>;
compatible = "brcm,brcmstb-i2c";
interrupt-parent = <&upg_irq0_intc>;
reg = <0x406280 0x58>;
interrupts = <25>;
interrupt-names = "upg_bscb";
status = "disabled";
};
bscc: i2c@406300 {
clock-frequency = <390000>;
compatible = "brcm,brcmstb-i2c";
interrupt-parent = <&upg_irq0_intc>;
reg = <0x406300 0x58>;
interrupts = <26>;
interrupt-names = "upg_bscc";
status = "disabled";
};
bscd: i2c@408980 {
clock-frequency = <390000>;
compatible = "brcm,brcmstb-i2c";
interrupt-parent = <&upg_aon_irq0_intc>;
reg = <0x408980 0x58>;
interrupts = <27>;
interrupt-names = "upg_bscd";
status = "disabled";
};
pwma: pwm@406400 {
compatible = "brcm,bcm7038-pwm";
reg = <0x406400 0x28>;
#pwm-cells = <2>;
clocks = <&upg_clk>;
status = "disabled";
};
pwmb: pwm@406700 {
compatible = "brcm,bcm7038-pwm";
reg = <0x406700 0x28>;
#pwm-cells = <2>;
clocks = <&upg_clk>;
status = "disabled";
};
aon_pm_l2_intc: interrupt-controller@408240 {
compatible = "brcm,l2-intc";
reg = <0x408240 0x30>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&periph_intc>;
interrupts = <50>;
brcm,irq-can-wake;
};
upg_gio: gpio@406500 {
compatible = "brcm,brcmstb-gpio";
reg = <0x406500 0xa0>;
#gpio-cells = <2>;
#interrupt-cells = <2>;
gpio-controller;
interrupt-controller;
interrupt-parent = <&upg_irq0_intc>;
interrupts = <6>;
brcm,gpio-bank-widths = <32 32 32 29 4>;
};
upg_gio_aon: gpio@408c00 {
compatible = "brcm,brcmstb-gpio";
reg = <0x408c00 0x60>;
#gpio-cells = <2>;
#interrupt-cells = <2>;
gpio-controller;
interrupt-controller;
interrupt-parent = <&upg_aon_irq0_intc>;
interrupts = <6>;
interrupts-extended = <&upg_aon_irq0_intc 6>,
<&aon_pm_l2_intc 5>;
wakeup-source;
brcm,gpio-bank-widths = <21 32 2>;
};
enet0: ethernet@430000 {
phy-mode = "internal";
phy-handle = <&phy1>;
mac-address = [ 00 10 18 36 23 1a ];
compatible = "brcm,genet-v2";
#address-cells = <0x1>;
#size-cells = <0x1>;
reg = <0x430000 0x4c8c>;
interrupts = <24>, <25>;
interrupt-parent = <&periph_intc>;
status = "disabled";
mdio@e14 {
compatible = "brcm,genet-mdio-v2";
#address-cells = <0x1>;
#size-cells = <0x0>;
reg = <0xe14 0x8>;
phy1: ethernet-phy@1 {
max-speed = <100>;
reg = <0x1>;
compatible = "brcm,40nm-ephy",
"ethernet-phy-ieee802.3-c22";
};
};
};
ehci0: usb@480300 {
compatible = "brcm,bcm7358-ehci", "generic-ehci";
reg = <0x480300 0x100>;
native-endian;
interrupt-parent = <&periph_intc>;
interrupts = <65>;
status = "disabled";
};
ohci0: usb@480400 {
compatible = "brcm,bcm7358-ohci", "generic-ohci";
reg = <0x480400 0x100>;
native-endian;
no-big-frame-no;
interrupt-parent = <&periph_intc>;
interrupts = <66>;
status = "disabled";
};
hif_l2_intc: interrupt-controller@411000 {
compatible = "brcm,l2-intc";
reg = <0x411000 0x30>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&periph_intc>;
interrupts = <30>;
};
nand: nand@412800 {
compatible = "brcm,brcmnand-v5.0", "brcm,brcmnand";
#address-cells = <1>;
#size-cells = <0>;
reg-names = "nand";
reg = <0x412800 0x400>;
interrupt-parent = <&hif_l2_intc>;
interrupts = <24>;
status = "disabled";
};
spi_l2_intc: interrupt-controller@411d00 {
compatible = "brcm,l2-intc";
reg = <0x411d00 0x30>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&periph_intc>;
interrupts = <31>;
};
qspi: spi@413000 {
#address-cells = <0x1>;
#size-cells = <0x0>;
compatible = "brcm,spi-bcm-qspi",
"brcm,spi-brcmstb-qspi";
clocks = <&upg_clk>;
reg = <0x410920 0x4 0x413200 0x188 0x413000 0x50>;
reg-names = "cs_reg", "hif_mspi", "bspi";
interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6>;
interrupt-parent = <&spi_l2_intc>;
interrupt-names = "spi_lr_fullness_reached",
"spi_lr_session_aborted",
"spi_lr_impatient",
"spi_lr_session_done",
"spi_lr_overread",
"mspi_done",
"mspi_halted";
status = "disabled";
};
mspi: spi@408a00 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "brcm,spi-bcm-qspi",
"brcm,spi-brcmstb-mspi";
clocks = <&upg_clk>;
reg = <0x408a00 0x180>;
reg-names = "mspi";
interrupts = <0x14>;
interrupt-parent = <&upg_aon_irq0_intc>;
interrupt-names = "mspi_done";
status = "disabled";
};
};
};
