/*
 * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

#include <arm/imx6qdl-phytec-pfla02.dtsi>

/ {
	memory {
		/* let barebox fill the memory node */
		reg = <0 0>;
	};

	chosen {
		environment-nand {
			compatible = "barebox,environment";
			device-path = &gpmi, "partname:barebox-environment";
			status = "disabled";
		};

		environment-spinor {
			compatible = "barebox,environment";
			device-path = &flash, "partname:barebox-environment";
			status = "disabled";
		};

		environment-sd1 {
			compatible = "barebox,environment";
			device-path = &usdhc1, "partname:barebox-environment";
			status = "disabled";
		};

		environment-sd2 {
			compatible = "barebox,environment";
			device-path = &usdhc2, "partname:barebox-environment";
			status = "disabled";
		};

		environment-sd3 {
			compatible = "barebox,environment";
			device-path = &usdhc3, "partname:barebox-environment";
			status = "disabled";
		};

		environment-sd4 {
			compatible = "barebox,environment";
			device-path = &usdhc4, "partname:barebox-environment";
			status = "disabled";
		};
	};
};

&ecspi3 {
	flash: flash@0 {
		#address-cells = <1>;
		#size-cells = <1>;

		partition@0 {
			label = "barebox";
			reg = <0x0 0x100000>;
		};

		partition@100000 {
			label = "barebox-environment";
			reg = <0x100000 0x20000>;
		};

		partition@120000 {
			label = "oftree";
			reg = <0x120000 0x20000>;
		};

		partition@140000 {
			label = "kernel";
			reg = <0x140000 0x0>;
		};
	};
};

&fec {
	phy-handle = <&ethphy>;
	phy-reset-duration = <10>; /* in msecs */

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy: ethernet-phy@3 {
			reg = <3>;

			txc-skew-ps = <1680>;
			rxc-skew-ps = <1860>;
		};
	};
};

&gpmi {
	#address-cells = <1>;
	#size-cells = <1>;

	partition@0 {
		label = "barebox";
		reg = <0x0 0x400000>;
	};

	partition@400000 {
		label = "barebox-environment";
		reg = <0x400000 0x100000>;
	};

	partition@500000 {
		label = "root";
		reg = <0x500000 0x0>;
	};
};

&iomuxc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_hog>, <&pinctrl_rev>;

	imx6q-phytec-pfla02 {
		pinctrl_rev: revgrp {
			fsl,pins = <
				MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x80000000
				MX6QDL_PAD_SD4_DAT4__GPIO2_IO12	0x80000000
				MX6QDL_PAD_SD4_DAT5__GPIO2_IO13	0x80000000
				MX6QDL_PAD_SD4_DAT6__GPIO2_IO14	0x80000000
				MX6QDL_PAD_SD4_DAT7__GPIO2_IO15	0x80000000
			>;
		};

		pinctrl_gpmi_nand: gpminandgrp {
			fsl,pins = <
				MX6QDL_PAD_NANDF_CLE__NAND_CLE     0xb0b1
				MX6QDL_PAD_NANDF_ALE__NAND_ALE     0xb0b1
				MX6QDL_PAD_NANDF_WP_B__NAND_WP_B   0xb0b1
				MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
				MX6QDL_PAD_NANDF_CS0__NAND_CE0_B   0xb0b1
				MX6QDL_PAD_NANDF_CS1__NAND_CE1_B   0xb0b1
				MX6QDL_PAD_NANDF_CS2__NAND_CE2_B   0xb0b1
				MX6QDL_PAD_NANDF_CS3__NAND_CE3_B   0xb0b1
				MX6QDL_PAD_SD4_CMD__NAND_RE_B      0xb0b1
				MX6QDL_PAD_SD4_CLK__NAND_WE_B      0xb0b1
				MX6QDL_PAD_NANDF_D0__NAND_DATA00   0xb0b1
				MX6QDL_PAD_NANDF_D1__NAND_DATA01   0xb0b1
				MX6QDL_PAD_NANDF_D2__NAND_DATA02   0xb0b1
				MX6QDL_PAD_NANDF_D3__NAND_DATA03   0xb0b1
				MX6QDL_PAD_NANDF_D4__NAND_DATA04   0xb0b1
				MX6QDL_PAD_NANDF_D5__NAND_DATA05   0xb0b1
				MX6QDL_PAD_NANDF_D6__NAND_DATA06   0xb0b1
				MX6QDL_PAD_NANDF_D7__NAND_DATA07   0xb0b1
				MX6QDL_PAD_SD4_DAT0__NAND_DQS      0x00b1
			>;
		};
	};
};

&ocotp {
	barebox,provide-mac-address = <&fec 0x620>;
};

&usdhc3 {
	#address-cells = <1>;
	#size-cells = <1>;

	partition@0 {
		label = "barebox";
		reg = <0x0 0xe0000>;
	};

	partition@e0000 {
		label = "barebox-environment";
		reg = <0xe0000 0x20000>;
	};
};

&i2c1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
	status = "okay";

	eeprom: eeprom@50 {
		compatible = "atmel,24c32";
		pagesize = <32>;
		reg = <0x50>;
	};
};