net: designware: eqos: don't funnel all MDIO writes to register 0
eqos_mdio_write ended up using the addr parameter instead of the
computed miiaddr variable, which would've factored in the reg parameter.

This had the effect that all writes went to PHY register 0, which was
fine as long as there were only register 0 writes. As soon there are more
writes, e.g. because a PHY driver was enabled, register 0 became
clobbered and erratic behavior ensued.
Fix the typo and while at it rename the val parameter to a more
descriptive name.

Fixes: a4f709bbb ("net: add Designware Ethernet QoS for STM32MP")
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
1 parent 6745b22 commit 70fcc51b1066d69b7042035d64e797eea5e75d6c
@Ahmad Fatoum Ahmad Fatoum authored on 17 Jan 2020
Sascha Hauer committed on 20 Jan 2020
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drivers/net/designware_eqos.c