Fix genphy_restart_aneg() for Micrel's ksz9031.
Commit da89ee8f2e04 ("Center FLP timing at 16ms") breaks
genphy_restart_aneg() for Micrel's ksz9031. According to the
datasheet, the ksz9031 requires a wait of 1ms after clearing
the PDOWN bit and before read/write access to any PHY registers.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
1 parent ad198ab commit a945a51b76fbbd19e912273952fb0b0401fcc564
@grodriguez grodriguez authored on 13 Jun 2016
Sascha Hauer committed on 14 Jun 2016
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drivers/net/phy/phy.c