watchdog: fix WATCHDOG_POLLER menuconfig ...

make it properly represented by menuconfig

Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

usb: imx: Do not disable VBUS on ehci_register()'s success ...

Original code was written to exit early on ehci_register()'s
success. As a part of e3eb0c729b, however, it was modified to to early
exit on failure instead. This resulted in VBUS being erroneously
disabled after EHCI controller was added, thus breaking USB on some
i.MX boards (confirmed on ZII's RDU2).

Fixes: e3eb0c729b ("usb: host: ehci: add ehci_unregister()")
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Cc: Vivien Didelot <vivien.didelot@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Merge branch 'for-next/rpi'

Merge branch 'for-next/pci'

Merge branch 'for-next/mmc-esdhc'

Merge branch 'for-next/misc'

Merge branch 'for-next/lseek'

Merge branch 'for-next/imx'

Merge branch 'for-next/e1000'

net: ethernet: cpsw: cpsw-phy-sel: Use phandle for phy sel ...

With the usage of the interconnect target module hierarchy in device tree the
cpsw-phy-sel node moved to the system control module. An phandle has
been added instead to the device tree include.

Try to use the cpsw-phy-sel phandle first then fall back looking for the
cpsw-phy-sel child.

This patch is based on the upstream kernel patch:
18eb8aea7fb2 ("net: ethernet: cpsw-phy-sel: prefer phandle for phy sel")

Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

drivers: of: Add function to enable and register a device by alias ...

In some cases node names are not unique and passing the full path is really long.
So make add a new device by passing the alias string possible.

Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

drivers: bus: Add ti-sysc bus driver ...

Adds minimal support for the sysc interconnect target module found
on many TI SoCs. With this device tree includes have been rearagned.
We need the driver to probe the child devices of the bus.

Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

nvmem: eeprom_93xx46: fix whitespaces ...

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

net: phy: micrel: backport ksz9031 125MHz ref-clk workaround ...

This patch backports linux commit e1b505a60366 ("net: phy: micrel: add
125MHz reference clock workaround").

8<--------------------- The original commit message -------------------

net: phy: micrel: add 125MHz reference clock workaround

The micrel KSZ9031 phy has a optional clock pin (CLK125_NDO) which can be
used as reference clock for the MAC unit. The clock signal must meet the
RGMII requirements to ensure the correct data transmission between the
MAC and the PHY. The KSZ9031 phy does not fulfill the duty cycle
requirement if the phy is configured as slave. For a complete
describtion look at the errata sheets: DS80000691D or DS80000692D.

The errata sheet recommends to force the phy into master mode whenever
there is a 1000Base-T link-up as work around. Only set the
"micrel,force-master" property if you use the phy reference clock provided
by CLK125_NDO pin as MAC reference clock in your application.

Attenation, this workaround is only usable if the link partner can
be configured to slave mode for 1000Base-T.

Signed-off-by: Markus Niebel <Markus.Niebel@tqs.de>
[m.felsch@pengutronix.de: fix dt-binding documentation]
[m.felsch@pengutronix.de: use already existing result var for read/write]
[m.felsch@pengutronix.de: add error handling]
[m.felsch@pengutronix.de: add more comments]
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
8<---------------------------------------------------------------------

Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

mci: imx-esdhc: Add layerscape support ...

This adds support for the esdhc controller found on Layerscape SoCs.
This means adding the compatible and a driver data to access the
controller in bigendian mode.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: imx6: Add support for i.MX8MQ ...

Port of a Linux commit 2d8ed46

  Add code needed to support i.MX8MQ variant.

  Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
  Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
  Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
  Cc: Bjorn Helgaas <bhelgaas@google.com>
  Cc: Fabio Estevam <fabio.estevam@nxp.com>
  Cc: Chris Healy <cphealy@gmail.com>
  Cc: Lucas Stach <l.stach@pengutronix.de>
  Cc: Leonard Crestez <leonard.crestez@nxp.com>
  Cc: "A.s. Dong" <aisheng.dong@nxp.com>
  Cc: Richard Zhu <hongxing.zhu@nxp.com>

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: imx6: Convert DIRECT_SPEED_CHANGE quirk code to use a flag ...

Port of a Linux commit 4c458bb

  Both i.MX7D and i.MX8MQ have the same behaviour when it comes to
  clearing DIRECT_SPEED_CHANGE bit when no speed change occurs, so to
  handle variants correctly add a flag instead of checking the IP block
  variant.

  Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
  [lorenzo.pieralisi@arm.com: updated log]
  Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
  Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
  Cc: Bjorn Helgaas <bhelgaas@google.com>
  Cc: Fabio Estevam <fabio.estevam@nxp.com>
  Cc: Chris Healy <cphealy@gmail.com>
  Cc: Lucas Stach <l.stach@pengutronix.de>
  Cc: Leonard Crestez <leonard.crestez@nxp.com>
  Cc: "A.s. Dong" <aisheng.dong@nxp.com>
  Cc: Richard Zhu <hongxing.zhu@nxp.com>

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: imx6: Mark PHY functions as i.MX6 specific ...

Port of a Linux commit 2f532d0

  PCIe PHY IP block on i.MX7D differs from the one used on i.MX6 family,
  so none of the code in the current implementation of
  imx6_setup_phy_mpll() or imx6_pcie_reset_phy() is applicable.

  Introduce IMX6_PCIE_FLAG_IMX6_PHY and check for it in the aforementioned
  functions to make sure they are only executed on appropriate PCIe IP
  variants.

  Tested-by: Trent Piepho <tpiepho@impinj.com>
  Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
  [lorenzo.pieralisi@arm.com: updated log]
  Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
  Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
  Cc: Bjorn Helgaas <bhelgaas@google.com>
  Cc: Fabio Estevam <fabio.estevam@nxp.com>
  Cc: Chris Healy <cphealy@gmail.com>
  Cc: Lucas Stach <l.stach@pengutronix.de>
  Cc: Leonard Crestez <leonard.crestez@nxp.com>
  Cc: "A.s. Dong" <aisheng.dong@nxp.com>
  Cc: Richard Zhu <hongxing.zhu@nxp.com>

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: imx6: Introduce drvdata ...

Port of a Linux commit e8e4d4e

  Introduce driver data struct. This will simplify handling of device
  specific differences.

  Signed-off-by: Stefan Agner <stefan@agner.ch>
  [andrew.smirnov@gmail.com reformatted drvdata, to simplify future diffs]
  Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
  Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
  Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
  Cc: Bjorn Helgaas <bhelgaas@google.com>
  Cc: Fabio Estevam <fabio.estevam@nxp.com>
  Cc: Chris Healy <cphealy@gmail.com>
  Cc: Lucas Stach <l.stach@pengutronix.de>
  Cc: Leonard Crestez <leonard.crestez@nxp.com>
  Cc: "A.s. Dong" <aisheng.dong@nxp.com>
  Cc: Richard Zhu <hongxing.zhu@nxp.com>

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

reset: imx7: Add support for i.MX8MQ IP block variant ...

Port of a Linux commit 34be9b4

  Add bits and pieces needed to support IP block variant found on
  i.MX8MQ SoCs.

  Cc: p.zabel@pengutronix.de
  Cc: Fabio Estevam <fabio.estevam@nxp.com>
  Cc: cphealy@gmail.com
  Cc: l.stach@pengutronix.de
  Cc: Leonard Crestez <leonard.crestez@nxp.com>
  Cc: "A.s. Dong" <aisheng.dong@nxp.com>
  Cc: Richard Zhu <hongxing.zhu@nxp.com>
  Cc: Rob Herring <robh@kernel.org>
  Cc: devicetree@vger.kernel.org
  Cc: linux-imx@nxp.com
  Cc: linux-arm-kernel@lists.infradead.org
  Cc: linux-kernel@vger.kernel.org
  Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

reset: imx7: Add plubming to support multiple IP variants ...

Port of a Linux commit cffaab8

  In order to enable supporting i.MX8MQ with this driver, convert it to
  expect variant specific bits to be passed via driver data.

  Cc: p.zabel@pengutronix.de
  Cc: Fabio Estevam <fabio.estevam@nxp.com>
  Cc: cphealy@gmail.com
  Cc: l.stach@pengutronix.de
  Cc: Leonard Crestez <leonard.crestez@nxp.com>
  Cc: "A.s. Dong" <aisheng.dong@nxp.com>
  Cc: Richard Zhu <hongxing.zhu@nxp.com>
  Cc: Rob Herring <robh@kernel.org>
  Cc: devicetree@vger.kernel.org
  Cc: linux-imx@nxp.com
  Cc: linux-arm-kernel@lists.infradead.org
  Cc: linux-kernel@vger.kernel.org
  Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

reset: Constify "ops" in struct reset_controller_dev ...

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

soc: imx: gpcv2: add support for i.MX8MQ SoC ...

Port of a Linux commit 685efff

  The GPCv2 on the Freescale i.MX8MQ SoC works in the same way as the
  GPCv2 on the i.MX7, but only controls more power domains with a
  different mapping.

  Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
  Acked-by: Rob Herring <robh@kernel.org>
  Signed-off-by: Shawn Guo <shawnguo@kernel.org>

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

soc: imx: gpcv2: prefix i.MX7 specific defines ...

Port of a Linux commit a800f41

  So we can add i.MX8M support without introducing name clashes.

  Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
  Signed-off-by: Shawn Guo <shawnguo@kernel.org>

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

soc: imx: gpcv2: Switch to SPDX identifier ...

Port of a Linux commit 8d8e3b7

  Adopt the SPDX license identifier headers to ease license compliance
  management.

  Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
  Signed-off-by: Shawn Guo <shawnguo@kernel.org>

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

soc: imx: gpcv2: make pgc driver more generic for other i.MX platforms ...

Port of a Linux commit 73f5971

  i.MX8MQ and i.MX8MM share same gpc module with i.MX7D, they
  can reuse gpcv2 pgc driver for power domain control, this
  patch renames all functions and structure definitions started
  with "imx7" to "imx", and use .data in imx_gpcv2_dt_ids[] to
  pass platform specific power domain data for power domain
  driver, thus make gpcv2 pgc driver more generic for i.MX
  platforms.

  Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
  Acked-by: Andrey Smirnov <andrew.smirnov@gmail.com>
  Signed-off-by: Shawn Guo <shawnguo@kernel.org>

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

soc: imx: gpcv2: use A_CORE instread of A7 for more i.MX platforms ...

Port of a Linux commit fea88b2

  gpcv2 driver is NOT just used on i.MX7D which has Cortex-A7
  cores, but also on i.MX8MQ/i.MX8MM platforms which use Cortex-A53
  cores, so let's use A_CORE instread of A7 to avoid confusion.

  Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
  Acked-by: Andrey Smirnov <andrew.smirnov@gmail.com>
  Signed-off-by: Shawn Guo <shawnguo@kernel.org>

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: dwc: Fix pointer width cast problem ...

Casting to u32 works well on 32-bit builds, but causes problem when
compiled on 64-bit machines. Switch it to cast to "unsigned long", so
that it would have appropriate width in both cases.

While at it, replace explicit casts to void * with IOMEM.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

net: fec_imx: skip fec_halt if the FEC wasn't started ...

If the FEC driver is enabled, but the ethernet device was never
opened due to booting from another source the wait for graceful
transmit stop will always fail. This introduces an unnecessary
boot delay and prints a distracting warning.

As there is no point in trying to shut down the FEC if it was
never started, just skip all of fec_halt in that case.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

net/e1000: Do not hardcode TDBAH and RDBAH to 0 ...

While there currently no user of e1000 driver that places those rings
beyond 4GiB boundary, there's also no real reason not to initialize
those registers properly.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>