ARM: i.MX6ul: Add SoC specific lowlevel_init function ...

On i.MX6ul(l) (Cortex A7) We have to set the SMP bit before
enabling the caches, otherwise they won't work. Add a SoC specific
lowlevel_init function to be called by the i.MX6ul(l) boards.

Since this is a quirk of the Cortex A7 core we put the functionality
into a separate function to be reused by other Cortex A7 cores.

Change existing i.MX6ul(l) boards to use the new initialisation
function. It seems this is only needed when booting from USB,
in other boot modes the ROM will already have done the initialisation.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

arm/cpu/lowlevel: fix: possible processor mode change ...

This is a re-application of fix 17644b55.
arm_cpu_lowlevel_init() will set the processor mode to 0x13 (supervisor).
When this function is entered via a different processor mode, register
banking will happen to lr (r14), resulting in an invalid return address.
This fix will preserve the return address manually.

Signed-off-by: Alexander Kurz <akurz@blala.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

arm/cpu/lowlevel: Don't save the return address in another register ...

The corresponding code doesn't use the lr register (neither explicitly
nor implicitly by the bl instruction), so there is no gain in using r2
here.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

arm/cpu/lowlevel: add and fix comments for CPSR and SCTLR accesses ...

A part of the existing comments was incomplete or missleading.
Adding the register name to mcr/mrc instructions helps finding the
corresponding documentation in the manuals.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

arm/cpu/lowlevel: invalidate i-cache before enabling ...

Architecturally the cache contents are undefined so it might well
contain stale data at reset. So better be save than sorry.

I verifyed that the added instructions are defined for both, ARMv6 and
ARMv7, using the ARM Architecture Reference Manual, ARMv7-A and ARMv7-R
edition (ARM DDI 0406C.c). For the already existing mcr instruction see
the newly added comment.

This patch also unifies handling of ARMv6 and ARMv7, the isb instruction
can also be done on the latter via mcr which simplifies the code a bit.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

bugfix: don't rely on lr in arm_cpu_lowlevel_init ...

Signed-off-by: 张忠山 <zzs213@126.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: Create an assembly arm_cpu_lowlevel_init function ...

To avoid the code duplication between the static inline C
function and the assembly macro.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>