This patch is based on a vendor patch in U-Boot, taken from
https://portland.source.codeaurora.org/patches/external/imxsupport/uboot-imx/imx_v2016.03_4.1.15_2.0.0_ga/HAB-238-Run-RNG-self-test-for-impacted-i.MX-chips.zip

|    HAB-238 Run RNG self test for impacted i.MX chips
|
|    Patch is only applicable to imx_v2016.03_4.1.15_2.0.0_ga branch of u-boot.
|    Please adapt the patch for your respective release version.
|
|    Background:
|    Few i.MX chips which have HAB 4.2.3 or beyond, have oberserved following
|    warning message generated by HAB due to incorrect implementation of drng
|    self test in boot ROM.
|
|        Event       |0xdb|0x0024|0x42| SRCE Field: 69 30 e1 1d
|                    |    |      |    |             STS = HAB_WARNING (0x69)
|                    |    |      |    |             RSN = HAB_ENG_FAIL (0x30)
|                    |    |      |    |             CTX = HAB_CTX_ENTRY (0xE1)
|                    |    |      |    |             ENG = HAB_ENG_CAAM (0x1D)
|                    |    |      |    | Evt Data (hex):
|                    |    |      |    |  00 08 00 02 40 00 36 06 55 55 00 03 00 00 00 00
|                    |    |      |    |  00 00 00 00 00 00 00 00 00 00 00 01
|
|    It is recommended to run this rng self test before any RNG related crypto
|    implementations are done.
|
[...]
|
|    Signed-off-by: Utkarsh Gupta <utkarsh.gupta@nxp.com>

Currently known impacted chips, as determined by NXP, include:
* i.MX6DQ+ silicon revision 1.1
* i.MX6DQ silicon revision 1.6
* i.MX6DLS silicon revision 1.4
* i.MX6SX silicon revision 1.4
* i.MX6UL silicon revision 1.2
* i.MX67SD silicon revision 1.3

Port the RNG software self-test from this patch to barebox. It can be
enabled by selecting CRYPTO_DEV_FSL_CAAM_RNG_SELF_TEST in Kconfig.

The original patch included a command line utility to run the self-test,
but we choose a different approach here, and run the software self-test
automatically when the respective HAB events indicating a RNG ROM
self-test failure are found when running habv4_get_status(). Note that
habv4_get_status() must be called by the board code before the CAAM
device driver is probed for this mechanism to work.

Until now there are at least two such known events. The first event was
observed on an i.MX6Solo, silicon revision 1.4; the second event is
mentioned in the original patch description given above. When an event
occured, habv4_get_status() tests if it is one of those known events,
and if so, indicates to the CAAM driver to run the software self-test.
In this case, printing the respective HAB warning is suppressed to
prevent confusion; the software self-test itself will error out in case
of recurring RNG self-test failure.

Signed-off-by: Roland Hieber <r.hieber@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Pick commit 654f2b9 from Linux
upstream.

    crypto: caam - allow retrieving 'era' from register

    The 'era' information can be retrieved from CAAM registers, so
    introduce a caam_get_era_from_hw() function that gets it via register
    reads in case the 'fsl,sec-era' property is not passed in the device
    tree.

    This function is based on the U-Boot implementation from
    drivers/crypto/fsl/sec.c

    Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
    Reviewed-by: Horia Geantă <horia.geanta@nxp.com>
    Tested-by: Breno Lima <breno.lima@nxp.com>
    Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Pick commit 261ea05 from Linux
upstream.

    crypto: caam - handle core endianness != caam endianness

    There are SoCs like LS1043A where CAAM endianness (BE) does not match
    the default endianness of the core (LE).
    Moreover, there are requirements for the driver to handle cases like
    CPU_BIG_ENDIAN=y on ARM-based SoCs.
    This requires for a complete rewrite of the I/O accessors.

    PPC-specific accessors - {in,out}_{le,be}XX - are replaced with
    generic ones - io{read,write}[be]XX.

    Endianness is detected dynamically (at runtime) to allow for
    multiplatform kernels, for e.g. running the same kernel image
    on LS1043A (BE CAAM) and LS2080A (LE CAAM) armv8-based SoCs.

    While here: debugfs entries need to take into consideration the
    endianness of the core when displaying data. Add the necessary
    glue code so the entries remain the same, but they are properly
    read, regardless of the core and/or SEC endianness.

    Note: pdb.h fixes only what is currently being used (IPsec).

    Reviewed-by: Tudor Ambarus <tudor-dan.ambarus@nxp.com>
    Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
    Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com>
    Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

As part of this patch rd_reg[8,16,32,64]() and wr_reg[8,16,32,64]()
helper functions are introduced. All readl() calls are replaced by
rd_reg32() and all writel() calls are replaced by wr_reg32().

Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Add the i.MX6 crypto core CAAM with support for the random number
generator.

The core itself works with jobrings in which descriptors can be
queued/dequeued for processing. Depending on descriptor type
the CAAM unit then either produces random numbers or decrypts/encrypts
data.

The code is based on the Linux v4.1 driver of the same name
without all the crypto/hashing components.

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>