We hard code memory size at three places:
 - In the configuration we use to initialize the DDRAM controller
 - In the minimal available size passed from PBL to barebox proper
 - In the device tree memory node override

Remove the two latter ones and replace them with code that reads the
size back from controller.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

When booting from SDMMC0, Use of SDMMC1 fails with:
ERROR: clk: couldn't set sdmmc1_gclk clk rate to 480000000 (-22), current rate: 32768

This is because the first stage bootloader only reparents the boot SDMMC
instance and barebox does no automatic reparenting for the other one.

Force both clocks to have a suitable parent.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

With Atmel SDHCI support incoming, we'll want the cards to have
predictable names. Extend the sama5d2.dtsi with an /aliases node.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Add hardware description, chip identification and clock changes to
support the sama5d2 SoC.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>