clk: imx: Add imx8mp clk driver ...

This adds clock support for the i.MX8MP, taken from Linux-5.7.

Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>

clk: migrate to SPDX-License-Identifier use ...

Some of these are a product of source sync with Linux, the other were
done with macro assistance by searching for /later/, deleting license text,
adding appropriate SPDX-License-Identifier and manual post-review.

Devices without a license indicated where assumed GPL-2.0-only according
with the project's license.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: imx: Add imx8mm clk driver ...

This adds clock support for the i.MX8MM, taken from Linux-5.5.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: imx: Add imx8m_clk_composite_critical ...

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: imx: Add pll14xx support ...

This adds support for the pll14xx found on i.MX8MM devices. This is
taken from the Kernel as of v5.5. Since we'll need some early setup
for the PLL a PBL hook is added to be called from lowlevel code.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: i.MX1: make locally used function static ...

mx1_clocks_init() is only used in one file, make it static.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: i.MX6ul: Disable GPMI_IO clk before reparenting ...

Before reparenting the ENFC_SEL mux we have to make sure the GPMI_IO clk
is disabled as recommended in the reference manual. Otherwise glitches
may occur on the GPMI clk which result in a later NAND failure:

MXS: Timeout resetting block via register 0x01806000
mxs_nand 1806000.gpmi-nand@1806000.of: probe failed: Connection timed out

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: i.MX6qp: Fix location of the enfc_sel mux ...

On the i.MX6qp the enfc_sel mux is at bits 15-17, not on 16-17. Fix
this. During clock tree initialization we reparented the enfc_sel to:

	clk_set_parent(clks[IMX6QDL_CLK_ENFC_SEL], clks[IMX6QDL_CLK_PLL2_PFD2_396M]);

This resulted in a register setting 0b110 for the enfc_sel mux which is
reserved. Apparently this reserved setting resulted in the enfc clock
being driven from pll3_pfd3_454m. This means our enfc clock was the
factor 454/396 too high.

With b534f79112f0 ("clk: imx6: Fix procedure to switch the parent of
LDB_DI_CLK") we happened to disable pll3_pfd3_454m during init, so with
this commit NAND stopped working entirely on i.MX6qp.

Both issues are fixed with this patch

Fixes: b534f79112f0 ("clk: imx6: Fix procedure to switch the parent of LDB_DI_CLK")
Fixes: 92fd61d12723 ("clk: i.MX6: Fix enfc_sel for i.MX6dqp")

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: imx6: define an enum for ldb mux inputs ...

For better readability should this code be reviewed
in future, replace the hardcoded input numbers
with an enum.

This is just a cosmetic change and was verified
to not affect clk-imx6.o.

Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Tested-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: imx6: Fix procedure to switch the parent of LDB_DI_CLK ...

Due to incorrect placement of the clock gate cell in the ldb_di[x]_clk
tree, the glitchy parent mux of ldb_di[x]_clk can cause a glitch to
enter the ldb_di_ipu_div divider. If the divider gets locked up, no
ldb_di[x]_clk is generated, and the LVDS display will hang when the
ipu_di_clk is sourced from ldb_di_clk.

To fix the problem, both the new and current parent of the ldb_di_clk
should be disabled before the switch. This patch ensures that correct
steps are followed when ldb_di_clk parent is switched in the beginning
of boot. The glitchy muxes are then registered as read-only. The clock
parent can be selected using the assigned-clocks and
assigned-clock-parents properties of the ccm device tree node:

        &clks {
                assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
                                  <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
                assigned-clock-parents = <&clks IMX6QDL_CLK_MMDC_CH1_AXI>,
                                         <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>;
        };

The issue is explained in detail in EB821 ("LDB Clock Switch Procedure &
i.MX6 Asynchronous Clock Switching Guidelines") [1].

[1] http://www.nxp.com/files/32bit/doc/eng_bulletin/EB821.pdf

Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@nxp.com>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Akshay Bhat <akshay.bhat@timesys.com>
Tested-by Joshua Clayton <stillcompiling@gmail.com>
Tested-by: Charles Kang <Charles.Kang@advantech.com.tw>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
[afa: reviewed for barebox]
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Tested-by: Andrey Smirnov <andrew.smirnov@gmail.com>
[afa: ported to barebox from Linux commit 5d283b0838]
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: imx6: Make the LDB_DI0 and LDB_DI1 clocks read-only ...

Based on Kernel commit 03d576f202 ("clk: imx6: Make the LDB_DI0 and LDB_DI1 clocks read-only"):

| Due to incorrect placement of the clock gate cell in the ldb_di[x]_clk
| tree, the glitchy parent mux of ldb_di[x]_clk can cause a glitch to
| enter the ldb_di_ipu_div divider. If the divider gets locked up, no
| ldb_di[x]_clk is generated, and the LVDS display will hang when the
| ipu_di_clk is sourced from ldb_di_clk.
|
| To fix the problem, both the new and current parent of the ldb_di_clk
| should be disabled before the switch. As this can not be guaranteed by
| the clock framework during runtime, make the ldb_di[x]_sel muxes read-only.
| A workaround to set the muxes once during boot could be added to the
| kernel or bootloader.
|
| Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
| Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
| Signed-off-by: Shawn Guo <shawnguo@kernel.org>

[afa: reviewed for barebox]
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Tested-by: Andrey Smirnov <andrew.smirnov@gmail.com>
[afa: ported from Linux kernel commit 03d576f202]
[afa: added exception for i.MX6QP, see kernel commit f4a0a6c309]
[afa: added cpu_has_err009219 helper function]
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: imx6: remove quirky clk_set_parent(LDB_diN_sel, pll5_video_div) ...

barebox has inherited the clk_set_parent(ldb_diN_sel, pll5_video_div)
from upstream kernel commit 32f3b8da22 ("ARM i.MX6q: set the LDB serial
clock parent to the video PLL"), where it was enabled for all i.MX6Q
revisions after 1.0. It was applied whenever CONFIG_DRIVER_VIDEO_IMX_IPUV3
was defined.

The kernel removed this reparenting again as a preventive measure
against ERR009219 in 03d576f202 ("clk: imx6: Make the LDB_DI0 and
LDB_DI1 clocks read-only").

In barebox, the reparenting remains and is done for all i.MX6 SoCs
with a revision > 1.0. On all of them, except for the QuadPlus and
the DualPlus, this reparenting may glitch the LDB so that it
permanently locks up.

By removing the reparenting in this commit, producing this glitch is
avoided. The device tree[1] can elect to reinstate the reparenting:

	&clks {
		assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
				  <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
		assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
					 <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>;
	};

Follow-up patches will explicitly check for this and do reparenting
defined this way in a glitch-free manner.

As of v2019.07.0, following mainline boards are potentially broken
by this (i.e. they're supported by barebox, are in the list above,
had a LDB enabled and might be defining CONFIG_DRIVER_VIDEO_IMX_IPUV3):
  - imx6qdl-zii-rdu2.dtsi
  - imx6qdl-udoo.dtsi
  - imx6qdl-mba6x.dtsi
  - imx6q-var-custom.dts
  - imx6q-guf-santaro.dts
  - imx6q-embedsky-e9.dtsi

[1]: If barebox is configured to show a boot splash screen, this snippet
     should exist in the barebox device tree. If barebox acts on it, the
     kernel will show following warning:
         ccm: ldb_di0_sel already changed from reset value: 0
         ccm: ldb_di1_sel already changed from reset value: 0
     This warning is safe to ignore.

Cc: Andrey Smirnov <andrew.smirnov@gmail.com>
Cc: Raphael Poggi <poggi.raph@gmail.com>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Tested-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: imx6: Mask mmdc_ch1 handshake for periph2_sel and mmdc_ch1_axi_podf ...

MMDC CH1 is not used on i.MX6Q, so the handshake needed to change the
parent of periph2_sel or the divider of mmdc_ch1_axi_podf will never
succeed.
Disable the handshake mechanism to allow changing the frequency of
mmdc_ch1_axi, allowing to use it as a possible source for the LDB DI
clock.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
[afa: reviewed for barebox]
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Tested-by: Andrey Smirnov <andrew.smirnov@gmail.com>
[afa: ported to barebox from Linux commit f13abeff2c]
[afa: moved call site to where it would've been moved in following commit]
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: imx6: fix use of cpu_is_mx6* before they are initialized ...

The cpu_is_mx6* macros rely on __imx_cpu_type, which is initialized
dependent on device tree compatible at "postcore" init-level imx_init.

The imx6q-ccm driver, which uses the cpu_is_mx6* macros, is registered
at "core" init-level, however. This results on the macro always returning
false.

Fix this by using the cpu_mx6_is_mx6* family of macros instead.
These already require that that CPU is a MX6, which is safe because the
the driver only matches against "fsl,imx6q-ccm".

Only exception is the video5 pll reparenting. Here we will just
maintain the old behavior as we will drop the if clause in a following
commit anyway.

Reported-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: imx: vf610: correct __iomem 'qualifier' placement ...

__iomem applies to the IOMEM() pointee, not to the auto pointer
that points at it. Move the annotation to correct this.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: vf610: improve handling case that cpu frequency can't be changed ...

Currently we get a nasty error message if the cpu clock can't be
changed:
DDRC is clocked by PLL1, can't switch CPU clockinitcall vf610_switch_cpu_clock+0x1/0x198 failed: Invalid argument

So let's do the following:
- factor out the check from vf610_switch_cpu_clock_to_500mhz() and
  vf610_switch_cpu_clock_to_400mhz
- if clock can't be changed, don't treat it as an error
- don't call clock notifier chain if clock can't be changed
- add trailing newline to the warning message

Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Reviewed-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: i.MX25: Add some more clocks ...

Add some clocks needed for:
- RNGB
- SCC
- Dryice RTC

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: mux: Support mux specific flags ...

We'll need mux specific flags in the future, so add a parameter to
the mux initialization functions.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: divider: pass divider flags ...

The generic clk divider needs clock flags and divider flags. Fix
prototypes to take both as separate arguments.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

treewide: Remove trailing whitespaces and tabs ...

Just a cleanup over barebox tree

Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: imx: sync imx8mq clock driver with upstream kernel ...

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: imx: add imx8mq composite clock ...

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: imx5: add di_pred ...

This was missing, so the default external DI clock source on i.MX51 was
missing. Also set the divider to a division ratio of 1 initially, to avoid
complicating the logic in the IPU driver further.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Merge branch 'for-next/missing-prototypes'

Merge branch 'for-next/imx'

clk: imx: cpu: avoid use after free on error ...

Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: i.MX5 clock: add clock provider support ...

Currently it is impossible to get clks with clk_get(&clk, "name");
on the mx5 platform. Change that by adding clk-imx5 as clk_provider.

Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: imx: Avoid missing prototype warnings ...

clk_gate2_free() is unused, so remove it. clk_gate2_alloc() is only
used locally, so make it static.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

drivers: clk: imx5: Make locally used functions static ...

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: i.MX8MQ: Add missing IMX8MQ_CLK_TMU_ROOT clock ...

Add missing IMX8MQ_CLK_TMU_ROOT clock needed for CPU thermal sensor.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>