mci: imx-esdhc-pbl: Add imx8mp_esdhc_load_image() for i.MX8MP ...

The image format of the i.MX8MP is different from i.MX8M, so add its own
image loading function for it.

Older i.MX SoCs had a IVT Offset (the offset from the start of the image
to the actual data) of 1KiB. This was done to leave space for the
partition table at the beginning of the device. To support GPT SoCs
starting with i.MX8M an additional gap of 32KiB was added, so that the
actual image started at offset 33KiB. Now starting with i.MX8MP the now
superfluous 1KiB offset was removed do that the actual image now starts
at 32KiB.
Unfortunately the 1KiB offset is woven into the offsets of the IVT
whereas the 32KiB are not, which means that we really have to handle
both offsets individually instead of just handling the sum of the
offsets.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

mci: imx-esdhc-pbl: Add instance 2 for i.MX8MM ...

Unlike the i.MX8MQ the i.MX8MM has three SDHCI controllers. Add support
for picking the base address of the third controller from the instance
number. While at it use the IMX8M_ base addresses rather than the
IMX8MQ_ base addresses.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: i.MX8M: rename functions to be i.MX8M specific ...

imx8_esdhc_load_image() and friends can't be used on the big variants of
the i.MX8, so rename to imx8m_esdhc_load_image()

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

esdhc-pbl: remove now unused imx8_esdhc_load_piggy ...

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

esdhc-pbl: allow to skip starting i.MX8 image ...

Add an option that allows to just load the image into memory, but
return to the calling function instead of directly jumping to the
loaded image.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

mci: imx-esdhc: Share code for esdhc_send_cmd() ...

Versions of esdhc_send_cmd() in imx-esdhc.c and imx-esdhc-pbl.c
implement almost the same algorithm. To avoid code repetition, move
that code to imx-esdhc-common.c and adjust all of the users
accordingly.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

mci: imx-esdhc: Introduce esdhc_poll() ...

Replace all of the explcitly coded timeout loops with a shared
subroutine that is used by both regular driver and PBL code.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

mci: imx-esdhc: Share code for esdhc_(setup|do)_data operations ...

PBL and PIO case of the regular driver do exaclty the same thing
during esdhc_(setup|do)_data stages of esdhc_send_cmd(). Move the code
to a common file and adjust all of the users accordingly.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

mci: imx-esdhc-pbl: Use sdhci_set_cmd_xfer_mode() ...

Drop extra code by converting imx-esdhc-pbl.c to use
sdhci_set_cmd_xfer_mode().

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

mci: imx-esdhc-pbl: Use sdhci_transfer_data() ...

Drop some extra code by converting esdhc_do_data() to use
sdhci_transfer_data().

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

mci: imx-esdhc-pbl: Share IO accessors with regular driver ...

With a bit of a change to PBL ESDHC initialization code it is possible
to share all of the low-level I/O accessor code with the regular
driver, including sharing definitions of flags describing HW's quirks.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

mci: imx-esdhc-pbl: Drop 'wrap_wml' flag ...

IMX_SDHCI_WML doesn't change its value during PBL opearation, so it
should be possible to configure it once. Doing it once also allows us
to move the call into SoC specific code making 'wrap_wml' flag
unnecessary.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

mci: imx-esdhc-pbl: Share initialization code ...

Move common ESDHC initialization code into subroutines and convert the
rest of the code to use it.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

mci: imx-esdhc-pbl: Don't setup DMA registers ...

PBL code is PIO only, so setting up DMA related registers shouldn't be
necessary.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

mci: sdhci: remove duplicate register defines for prsstat bits ...

We have duplicate register bit defines for the prsstat register.
Remove the duplicates.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

mci: sdhci: remove duplicate register defines for interrupt bits ...

We have duplicate bit defines for the interrupt bits. Remove the duplicates.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

mci: sdhci: remove duplicate transfer mode register defines ...

We have duplicate register bit defines for the transfer mode register.
Remove the duplicates.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

mci: imx-esdhc-pbl: Use 16bit register definitions ...

We have some register defines in a 16bit access version and a 32bit
access version. Use the former to get rid of the latter later.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

mci: imx-esdhc-pbl: Fix watermark level value for i.MX ...

Layerscape and i.MX have different semantics of Watermark Level
Register. Whereas the former uses "0" to signify maximum allowed
value, the latter does not.

According to the RM (i.MX8MQ, i.MX6):

"...The read burst length must be less than or equal to the read
watermark level.."

Setting Watermark Level Register to zero violates that limitation. It
appears that, on i.MX8MQ, not following that rule causes certain
configs + toolchains to result in non-bootable image. Specifically,
polling for CICHB, CIDHB and DLA to clear in esdhc_send_cmd() times
out. There doesn't appear to be any clear relationship as to what kind
of image will have the problem, but the following combinations failed
to boot on ZII i.MX8MQ Zest board:

  - gcc version 9.2.1 20190827 (Red Hat Cross 9.2.1-1) (GCC) +
    imx_v8_defconfig + CONFIG_DEBUG_LL and CONFIG_PBL_CONSOLE

  - gcc version 5.5.0 (Timesys 20190405) (custom toolchain) +
    imx_v8_defconfig

Setting WML's *_BRST_LE to 16 and *_WML to 128 on i.MX resolves the
issue (same setting that's selected by writing 0 on Layerscape).

Fixes: 48562aeaa8 ("esdhc-xload: check for PRSSTAT_BREN only after each block")
Cc: Chris Healy <cphealy@gmail.com>
Cc: Ruslan Sushko <ruslan.sushko@zii.aero>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Tested-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: i.MX8: Fix piggydata loading ...

We are running at MX8MQ_ATF_BL33_BASE_ADDR now, so we can't use
this as a temporary buffer. Add 32MiB to that address and use this
instead. Also copy the piggydata to the place where we expect it
later.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Reviewed-by: Rouven Czerwinski <r.czerwinski@pengutronix.de>

esdhc-pbl: add piggy load function ...

Add a function to load and copy the piggy data to the correct offset
expected by barebox in the RAM. This way the PBL can later verify the
piggydata before uncompressing and loading the main barebox.

Signed-off-by: Rouven Czerwinski <r.czerwinski@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

esdhc-pbl: extract header parsing from image start ...

Extract the header parsing code from esdc_start_image. The header
parsing function will be used by the piggy loading code added in the
next commit.

Signed-off-by: Rouven Czerwinski <r.czerwinski@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: introduce sync_caches_for_execution ...

We have several places in the code which which prepares just modified code
for execution. This is done differently in all the places, so add a common
function to be used by all.

Most places called arm_early_mmu_cache_flush(). This function includes
invalidating the instruction cache, so doing it again is unnecessary.

Sometimes we had arm_early_mmu_cache_flush() inside #ifdef CONFIG_MMU.
The ifdef seems unnecessary since we do not have it consistently, so
remove the ifdef.

Some early i.MX xload code had icache_invalidate() but forgot to flush
the caches. Replace the instruction cache invalidation with
sync_caches_for_execution().

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

esdhc-xload: invalidate icache before jumping to image ...

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

mci: imx-esdhc-pbl: ls1046a: Set better divider values ...

MMC Frequency was set to something like 55MHz. This doesn't work for all
SD cards. Set to 25MHz which is supported by all SD cards.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Merge branch 'for-next/layerscape'

mci: imx-esdhc-pbl: initialize is_be ...

Initialize is_be, otherwise the value of is_be is undefined.
So it is possible that the i.MX8 will not boot because the bigendian
functions are used.

Signed-off-by: Christian Hemp <c.hemp@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

esdhc-xload: Add support for Layerscape ...

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

esdhc-xload: check for PRSSTAT_BREN only after each block ...

The BREN bit tells us a watermark level sized buffer is ready for read.
Instead of testing it before each FIFO read we must only check it once
and then read a watermark level sized buffer. This is at least necessary
on Layerscape, otherwise timeouts occur while reading the buffer.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

esdhc-xload: Add bigendian support ...

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>