PCI: dwc: Sync register definitions with Linux-5.4 ...

Update the dwc register definitions with Linux-5.4 to make further
syncinf with the Linux driver easier.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: dwc: rename readl/writel_dbi ops to read/write_dbi ...

struct dw_pcie_ops read/writel_dbi functions can read values of any
size, so with readl/writel they are misnamed. Rename them to read/write
which also matches the kernel driver.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: dwc: Cleanup DBI,ATU read and write APIs ...

Port of Linux commit 7bc082d

    Cleanup DBI read and write APIs by removing leading "__" (underscore)
    from their names as there is no reason to have leading underscores
    in the first place in the function definition.

    Remove dbi/dbi2 base address parameters as the same behaviour can be
    obtained through read and write APIs. Since dw_pcie_{readl/writel}_dbi()
    APIs can't be used for ATU read/write as ATU base address could be
    different from DBI base address, implement ATU read/write APIs using ATU
    base address without using dw_pcie_{readl/writel}_dbi() APIs.

    Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
    Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
    Acked-by: Jingoo Han <jingoohan1@gmail.com>

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: dwc: imx6: Share PHY debug register definitions ...

Port of Linux commit 60ef4b0

    Both pcie-designware.c and pci-imx6.c contain custom definitions for
    PHY debug registers R0/R1 and on top of that there's already a
    definition for R0 in pcie-designware.h. Move all of the definitions to
    pcie-designware.h. No functional change intended.

    Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
    Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
    Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
    Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
    Cc: Bjorn Helgaas <bhelgaas@google.com>
    Cc: Chris Healy <cphealy@gmail.com>
    Cc: Lucas Stach <l.stach@pengutronix.de>
    Cc: linux-kernel@vger.kernel.org
    Cc: linux-pci@vger.kernel.org

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: dwc: Fix ATU identification for designware version >= 4.80 ...

Port of Linux commit 2aadcb0

    Synopsys designware version >= 4.80 uses a separate register space
    for programming ATU. The current code identifies if there exists a
    separate register space by accessing the register address of ATUs
    in designware version < 4.80. Accessing this address results in
    abort in the case of K2G.

    Fix it here by adding "version" member to struct dw_pcie. This should be
    set by platform specific drivers and designware core will use it to
    identify if the platform has a separate ATU space. For platforms which
    have not populated the version member, the old method of identification
    will still be used.

    Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
    Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: dwc: Make use of BIT() in constant definitions ...

Port of Linux commit 0e11faa

    Avoid using explicit left shifts and convert various definitions to
    use BIT() instead. No functional change intended.

    Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
    [lorenzo.pieralisi@arm.com: fixed PORT_LOGIC_SPEED_CHANGE redefinition]
    Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
    Acked-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
    Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
    Cc: Bjorn Helgaas <bhelgaas@google.com>
    Cc: Fabio Estevam <fabio.estevam@nxp.com>
    Cc: Chris Healy <cphealy@gmail.com>
    Cc: Lucas Stach <l.stach@pengutronix.de>
    Cc: Leonard Crestez <leonard.crestez@nxp.com>
    Cc: "A.s. Dong" <aisheng.dong@nxp.com>
    Cc: Richard Zhu <hongxing.zhu@nxp.com>
    Cc: linux-imx@nxp.com
    Cc: linux-arm-kernel@lists.infradead.org
    Cc: linux-kernel@vger.kernel.org
    Cc: linux-pci@vger.kernel.org

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: dwc: Add dw_pcie_disable_atu() ...

This adds dw_pcie_disable_atu() taken from Linux-5.4. This is needed by
the upcoming Layerscape driver.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: dwc: Don't hard-code DBI/ATU offset ...

Port of Linux commit 6d6b05e

    The DWC PCIe core contains various separate register spaces: DBI, DBI2,
    ATU, DMA, etc. The relationship between the addresses of these register
    spaces is entirely determined by the implementation of the IP block, not
    by the IP block design itself. Hence, the DWC driver must not make
    assumptions that one register space can be accessed at a fixed offset from
    any other register space. To avoid such assumptions, introduce an
    explicit/separate register pointer for the ATU register space. In
    particular, the current assumption is not valid for NVIDIA's T194 SoC.

    The ATU register space is only used on systems that require unrolled ATU
    access. This property is detected at run-time for host controllers, and
    when this is detected, this patch provides a default value for atu_base
    that matches the previous assumption re: register layout. An alternative
    would be to update all drivers for HW that requires unrolled access to
    explicitly set atu_base. However, it's hard to tell which drivers would
    require atu_base to be set. The unrolled property is not detected for
    endpoint systems, and so any endpoint driver that requires unrolled access
    must explicitly set the iatu_unroll_enabled flag (none do at present), and
    so a check is added to require the driver to also set atu_base while at
    it.

    Signed-off-by: Stephen Warren <swarren@nvidia.com>
    Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
    Acked-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
    Acked-by: Vidya Sagar <vidyas@nvidia.com>

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: dwc: Constify dw_pcie_host_ops structures ...

Port of a Linux commit 4ab2e7c

  The dw_pcie_host_ops structures are never modified.  Constify these
  structures such that these can be write-protected.

  Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
  Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
  Acked-by: Jingoo Han <jingoohan1@gmail.com>
  Acked-by: Kishon Vijay Abraham I <kishon@ti.com>

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: dwc: Add accessors for write permission of DBI ...

Port of a Linux commit e44abfe

  The read-only DBI registers can be written only when the "Write to RO
  Registers Using DBI" (DBI_RO_WR_EN) field of MISC_CONTROL_1_OFF is set.

  Add accessors to enable and disable write permission, and use them instead
  of accessing MISC_CONTROL_1_OFF directly.

  Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
  Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
  Acked-by: Joao Pinto <jpinto@synopsys.com>
  Acked-by: Roy Zang <tie-fei.zang@freescale.com>

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: dwc: designware: Handle ->host_init() failures ...

Port of a Linux commit 4a30176

  In several dwc-based drivers, ->host_init() can fail, so make sure to
  propagate and handle this to avoid continuing operation of a driver or
  hardware in an invalid state.

  Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
  Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
  Acked-by: Joao Pinto <jpinto@synopsys.com>
  Acked-by: Jingoo Han <jingoohan1@gmail.com>

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: Add SPDX GPL-2.0 to replace GPL v2 boilerplate ...

Port of a Linux commit 8cfab3c

  Add SPDX GPL-2.0 to all PCI files that specified the GPL version 2 license.

  Remove the boilerplate GPL version 2 language, relying on the assertion in
  b24413180f56 ("License cleanup: add SPDX GPL-2.0 license identifier to
  files with no license") that the SPDX identifier may be used instead of the
  full boilerplate text.

  Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
  Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: Fix typos and whitespace errors ...

Port of a Linux commit 96291d5

  Fix various typos and whitespace errors:

    s/Synopsis/Synopsys/
    s/Designware/DesignWare/
    s/Keystine/Keystone/
    s/gpio/GPIO/
    s/pcie/PCIe/
    s/phy/PHY/
    s/confgiruation/configuration/

  No functional change intended.

  Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: dwc: all: Modify dbi accessors to access data of 4/2/1 bytes ...

Port of a Linux commit a509d7d

  Previously dbi accessors can be used to access data of size 4 bytes. But
  there might be situations (like accessing MSI_MESSAGE_CONTROL in order to
  set/get the number of required MSI interrupts in EP mode) where dbi
  accessors must be used to access data of size 2. This is in preparation
  for adding endpoint mode support to designware driver.

  Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
  Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
  Acked-by: Niklas Cassel <niklas.cassel@axis.com>
  Cc: Jingoo Han <jingoohan1@gmail.com>
  Cc: Joao Pinto <Joao.Pinto@synopsys.com>

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: dwc: all: Modify dbi accessors to take dbi_base as argument ...

Port of a Linux commit b50b2db

  dwc has 2 dbi address space labeled dbics and dbics2. The existing helper
  to access dbi address space can access only dbics. However dbics2 has to
  be accessed for programming the BAR registers in the case of EP mode. This
  is in preparation for adding EP mode support to dwc driver.

  Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
  Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
  Acked-by: Niklas Cassel <niklas.cassel@axis.com>
  Cc: Jingoo Han <jingoohan1@gmail.com>
  Cc: Joao Pinto <Joao.Pinto@synopsys.com>

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: dwc: Split pcie-designware.c into host and core files ...

Port of a Linux commit feb85d9

  Split pcie-designware.c into pcie-designware-host.c that contains the host
  specific parts of the driver and pcie-designware.c that contains the parts
  used by both host driver and endpoint driver.

  Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
  Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: dwc: designware: Parse "num-lanes" property in dw_pcie_setup_rc() ...

Port of a Linux commit 5f334db

  The "num-lanes" DT property is parsed in dw_pcie_host_init(). However
  num-lanes is applicable to both root complex mode and endpoint mode. As a
  first step, move the parsing of this property outside dw_pcie_host_init().
  This is in preparation for splitting pcie-designware.c to pcie-designware.c
  and pcie-designware-host.c

  Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
  Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: dwc: all: Split struct pcie_port into host-only and core structures ...

Port of a Linux commit 442ec4c

  Keep only the host-specific members in struct pcie_port and move the common
  members (i.e common to both host and endpoint) to struct dw_pcie.  This is
  in preparation for adding endpoint mode support to designware driver.

  While at that also fix checkpatch warnings.

  Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
  Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
  CC: Jingoo Han <jingoohan1@gmail.com>
  CC: Richard Zhu <hongxing.zhu@nxp.com>
  CC: Lucas Stach <l.stach@pengutronix.de>
  CC: Murali Karicheri <m-karicheri2@ti.com>
  CC: Minghuan Lian <minghuan.Lian@freescale.com>
  CC: Mingkai Hu <mingkai.hu@freescale.com>
  CC: Roy Zang <tie-fei.zang@freescale.com>
  CC: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  CC: Niklas Cassel <niklas.cassel@axis.com>
  CC: Jesper Nilsson <jesper.nilsson@axis.com>
  CC: Joao Pinto <Joao.Pinto@synopsys.com>
  CC: Zhou Wang <wangzhou1@hisilicon.com>
  CC: Gabriele Paoloni <gabriele.paoloni@huawei.com>
  CC: Stanimir Varbanov <svarbanov@mm-sol.com>
  CC: Pratyush Anand <pratyush.anand@gmail.com>

For convenience sake, commit c046406

  PCI: dwc: Fix crashes seen due to missing assignments

  Fix the following crash, seen in dwc/pci-imx6.

    Unable to handle kernel NULL pointer dereference at virtual address 00000070
    pgd = c0004000
    [00000070] *pgd=00000000
    Internal error: Oops: 805 [#1] SMP ARM
    Modules linked in:
    CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.10.0-09686-g9e31489 #1
    Hardware name: Freescale i.MX6 Quad/DualLite (Device Tree)
    task: cb850000 task.stack: cb84e000
    PC is at imx6_pcie_probe+0x2f4/0x414
    ...

  While at it, fix the same problem in various drivers instead of waiting for
  individual crash reports.

  The change in the imx6 driver was tested with qemu. The changes in other
  drivers are based on code inspection and have been compile tested only.

  Fixes: 442ec4c04d12 ("PCI: dwc: all: Split struct pcie_port into host-only and core structures")
  Signed-off-by: Guenter Roeck <linux@roeck-us.net>
  Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org>  # designware-plat
  Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
  Acked-by: Kishon Vijay Abraham I <kishon@ti.com>

was squashed into this one as well.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: dwc: all: Rename cfg_read/cfg_write to read/write ...

No functional change. dw_pcie_cfg_read()/dw_pcie_cfg_write() doesn't do
  anything specific to access configuration space. It can be just renamed to
  dw_pcie_read()/dw_pcie_write() and used to read/write data to dbi space.

  Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
  Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
  Reviewed-By: Joao Pinto <jpinto@synopsys.com>
  CC: Jingoo Han <jingoohan1@gmail.com>
  CC: Murali Karicheri <m-karicheri2@ti.com>
  CC: Stanimir Varbanov <svarbanov@mm-sol.com>
  CC: Pratyush Anand <pratyush.anand@gmail.com>

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: dwc: designware: Move register defines to designware header file ...

Port of a Linux commmit b90dc39

  No functional change. Move the register defines and other macros from
  pcie-designware.c to pcie-designware.h. This is in preparation to split the
  pcie-designware.c file into designware core file and host-specific file.

  While at that also fix a checkpatch warning.

  Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
  Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
  Reviewed-By: Joao Pinto <jpinto@synopsys.com>

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: designware: Export dw_pcie_readl_rc(), dw_pcie_writel_rc() ...

Export dw_pcie_readl_rc() and dw_pcie_writel_rc().  Many other drivers can
  use these instead of implementing their own versions.  No functional change
  intended.

  Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: designware: Swap order of dw_pcie_writel_rc() reg/val arguments ...

Port of a Linux commit ad88021

  Swap order of dw_pcie_writel_rc() arguments to match the "dev, pos, val"
  order used by pci_write_config_word() and other drivers.  No functional
  change intended.

  Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: designware: Simplify pcie_host_ops.readl_rc() and .writel_rc() interfaces ...

Port of a Linux commit 7e00dfd

  The struct pcie_host_ops.readl_rc() and .writel_rc() function pointers
  allow a driver to override the default DesignWare register accessors.

  Make the signature of the override functions the same as the default
  accessors.  This makes the default dw_pcie_readl_rc() and the corresponding
  override more structurally similar: both will compute the final register
  address with "pp->dbi_base + reg".  Previously dw_pcie_readl_rc() computed
  the address and passed it to the override.

  No functional change intended.

  Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: designware: Keep viewport fixed for IO transaction if num_viewport > 2 ...

Port of a Linux commit fe48cb8

  Most of the platforms have 3 or more viewports.  For such platforms, We do
  not need to share viewports between IO and CFG.  Assign viewport 2 to IO
  transactions in such cases.

  Tested-by: Dong Bo <dongbo4@huawei.com>
  Signed-off-by: Pratyush Anand <pratyush.anand@gmail.com>
  Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
  Acked-by: Rob Herring <robh@kernel.org>

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: designware: Add iATU Unroll feature ...

Port of a Linux commit a0601a4

  Add support for the new iATU Unroll mechanism that will be used from Core
  version 4.80.  The new Cores can support either iATU Unroll or the "old"
  iATU method, now called Legacy Mode.  The driver is perfectly capable of
  performing well for both.

  [bhelgaas: split ATU enable timeout to separate patch]
  Signed-off-by: Joao Pinto <jpinto@synopsys.com>
  Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

To avoid breaking i.MX6 PCIE support commit
416379f was squashed here as well

  PCI: designware: Check for iATU unroll support after initializing host

  dw_pcie_iatu_unroll_enabled() reads a dbi_base register.  Reading any
  dbi_base register before pp->ops->host_init has been called causes
  "imprecise external abort" on platforms like ARTPEC-6, where the PCIe
  module is disabled at boot and first enabled in pp->ops->host_init.  Move
  dw_pcie_iatu_unroll_enabled() to dw_pcie_setup_rc(), since it is after
  pp->ops->host_init, but before pp->iatu_unroll_enabled is actually used.

  Fixes: a0601a470537 ("PCI: designware: Add iATU Unroll feature")
  Tested-by: James Le Cuirot <chewi@gentoo.org>
  Signed-off-by: Niklas Cassel <niklas.cassel@axis.com>
  Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
  Acked-by: Joao Pinto <jpinto@synopsys.com>
  Acked-by: Olof Johansson <olof@lixom.net>

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: designware: Move link wait definitions to .c file ...

Port of a Linux commit c388de1

  Move the link wait sleep definitions to the .c file as suggested by
  Jisheng Zhang in a previous patch.

  Signed-off-by: Joao Pinto <jpinto@synopsys.com>
  Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
  CC: Jisheng Zhang <jszhang@marvell.com>

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: designware: Return data directly from dw_pcie_readl_rc() ...

Port of a Linux commit 446fc23

  dw_pcie_readl_rc() reads a u32 value.  Previously we stored that value in
  space supplied by the caller.  Return the u32 value directly instead.

  This makes the calling code read better and makes it obvious that the
  caller need not initialize the storage.  In the following example it isn't
  clear whether "val" is initialized before being used:

    dw_pcie_readl_rc(pp, PCI_COMMAND, &val);
    if (val & PCI_COMMAND_MEMORY)
      ...

  No functional change intended.

  Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: designware: Add generic dw_pcie_wait_for_link() ...

Port of Linux commit 886bc5c

  Several DesignWare-based drivers (dra7xx, exynos, imx6, keystone, qcom, and
  spear13xx) had similar loops waiting for the link to come up.

  Add a generic dw_pcie_wait_for_link() for use by all these drivers so the
  waiting is done consistently, e.g., always using usleep_range() rather than
  mdelay() and using similar timeouts and retry counts.

  Note that this changes the Keystone link training/wait for link strategy,
  so we initiate link training, then wait longer for the link to come up
  before re-initiating link training.

  [bhelgaas: changelog, split into its own patch, update pci-keystone.c, pcie-qcom.c]
  Signed-off-by: Joao Pinto <jpinto@synopsys.com>
  Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
  Acked-by: Pratyush Anand <pratyush.anand@gmail.com>

NOTE: For some reason, all of the changes to imx6_pcie_wait_for_link()
made in 4d107d3 are actually not
present 886bc5c. So there isn't
really a kernel commit corresponding to removal of the large comment
block or check for !(reg & PCIE_PHY_DEBUG_R1_XMLH_LINK_IN_TRAINING)

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: designware: Simplify dw_pcie_cfg_read/write() interfaces ...

Port of a Linux commit 4c45852

  Callers of dw_pcie_cfg_read() and dw_pcie_cfg_write() previously had to
  split the address into "addr" and "where".  The callees assumed "addr" was
  32-bit aligned (with zeros in the low two bits) and they used only the low
  two bits of "where".

  Accept the entire address in "addr" and drop the now-redundant "where"
  argument.  As an example, this replaces this:

    int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val)
      *val = readb(addr + (where & 1));

  with this:

    int dw_pcie_cfg_read(void __iomem *addr, int size, u32 *val)
      *val = readb(addr):

  [bhelgaas: changelog, split access size change to separate patch]
  Signed-off-by: Gabriele Paoloni <gabriele.paoloni@huawei.com>
  Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

TODO: Fixup the pcie-designware.h

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: desginware: Remove bogus prototypes ...

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>