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History for barebox / arch

2018-08-08	4ff0c3f Browse files » ARM: arria10: update defconfig ... Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Steffen Trumtrar authored on 31 Jul 2018 Sascha Hauer committed on 8 Aug 2018
	21fbe47 Browse files » ARM: socfpga: achilles: convert to PBL barebox ... Previously the FPGA was configured externally on the Achilles. On newer versions this is changed and barebox has to configure the FPGA before the SDRAM can be used. If the FPGA is configured via JTAG or from an external memory, the *-bringup version can be used. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Steffen Trumtrar authored on 31 Jul 2018 Sascha Hauer committed on 8 Aug 2018
	8a680e3 Browse files » ARM: socfpga: Arria10: support programming FPGA in PBL ... Some Arria10 boards don't have the FPGA programmed externally. Instead barebox needs to do that. As the Arria10 has the SDRAM controller in the FPGA, the first thing we need to do is, configure the FPGA before the SDRAM can even be used. It works like this: 1. boot ROM fetches the PBL from MMC 2. read the MBR from MMC (this depends on the setup done by the boot ROM) 3. read the Bitstream from the MMC and program the FPGA 4. re-read the barebox image from MMC, this time with the full barebox that is appended to the PBL 5. jump into the full barebox Only supported boot device is eMMC. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Steffen Trumtrar authored on 31 Jul 2018 Sascha Hauer committed on 8 Aug 2018
	1466d7d Browse files » ARM: socfpga: arria10-reset-manager: don't reset bootsource ... Arria10 init code resets all peripherals. Convert this to keep the bootmedium out of reset and keep the setup done by the boot ROM. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Steffen Trumtrar authored on 31 Jul 2018 Sascha Hauer committed on 8 Aug 2018
	d916ae1 Browse files » ARM: dts: socfpga: Fix achilles dtc warnings ... The newer dtc has stricter checks on devicetrees. Fix the warnings. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Steffen Trumtrar authored on 31 Jul 2018 Sascha Hauer committed on 8 Aug 2018
	bc8adf6 Browse files » ARM: socfpga: achilles: update handoff files ... Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Steffen Trumtrar authored on 31 Jul 2018 Sascha Hauer committed on 8 Aug 2018
	6e147fb Browse files » ARM: socfpga: arria10: fix SDMMC phase shift ... Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Steffen Trumtrar authored on 31 Jul 2018 Sascha Hauer committed on 8 Aug 2018
	d81a1ba Browse files » ARM: socfpga: arria10: set default TEXTBASE ... Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Steffen Trumtrar authored on 31 Jul 2018 Sascha Hauer committed on 8 Aug 2018
	4418dd9 Browse files » ARM: socfpga: arria10-init: split pinsetup ... Move the setup of the shared- and fpgapins to its own function. These pins can only be configured and let out of reset after the FPGA has been programmed. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Steffen Trumtrar authored on 31 Jul 2018 Sascha Hauer committed on 8 Aug 2018
	98152c3 Browse files » ARM: socfpga: add SMP_TWD_ADDR for Arria10 ... Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Steffen Trumtrar authored on 31 Jul 2018 Sascha Hauer committed on 8 Aug 2018
	3927ffb Browse files » ARM: socfpga: arria10: add ocram base address ... Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Steffen Trumtrar authored on 31 Jul 2018 Sascha Hauer committed on 8 Aug 2018
	54800ba Browse files » ARM: socfpga: arria10: move debug_ll to common code ... Instead of copy+pasting the debug_ll messages to every new board, move them to the respective functions. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Steffen Trumtrar authored on 31 Jul 2018 Sascha Hauer committed on 8 Aug 2018
	5296431 Browse files » bootm: allow booting SoCFPGA prebootloader image ... A prebootloader image might also contain a fully working barebox and allows to be booted second stage. Thus we add a handler here to give it a try. Signed-off-by: Enrico Jorns <ejo@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Enrico Jorns authored on 31 Jul 2018 Sascha Hauer committed on 8 Aug 2018
	6d1b29b Browse files » ARM: i.MX: fix compilation with BBU disabled ... Make a static inline wrapper actually static inline. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Sascha Hauer committed on 8 Aug 2018
	2454615 Browse files » ARM: i.MX8MQ: Add code to load BL31 ATF blob ... Add imx8mq_atf_load_bl31() containing all of the code needed to load and transfer control to BL31 ATF blob on i.MX8M. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Andrey Smirnov authored on 19 Jul 2018 Sascha Hauer committed on 8 Aug 2018
	34b808b Browse files » ARM: i.MX8MQ: Configure cntfrq only in EL3 ... We only can (and should only need to) configure cntfrq when running in EL3 and executing this code in any other exception level will result in exception. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Andrey Smirnov authored on 19 Jul 2018 Sascha Hauer committed on 8 Aug 2018
	2c20674 Browse files » ARM: Add code to support SMCCC on AArch64 ... Port SMCCC code from Linux kernel. To accomodate that: - Introduce CONFIG_ARM_SMCCC, to allow enabling the code independent of CONFIG_ARM_SECURE_MONITOR - Bring <linux/arm-smccc.h> in - Add necessary constants to arch/arm/asm-offsets.c Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Andrey Smirnov authored on 19 Jul 2018 Sascha Hauer committed on 8 Aug 2018
	e70be9e Browse files » ARM: nxp-imx8mq-evk: Update DDR initialization code ... Previous version of DDR initialization code was generated by a beta version of MX8_DDR_tool. This updates the code to the output of MX8_DDR_tool v1.0, which seem to fix the vendor Linux kernel hang* that was happening with the previous version. * The kernel would hang as soon as it tried to utilize DDR's DVFS features and switch DDR frequency (disabling busfreq-imx8mq.c would fix the problem). Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Andrey Smirnov authored on 19 Jul 2018 Sascha Hauer committed on 8 Aug 2018
2018-08-06	8cd0c69 Browse files » ARM: i.MX: fix compilation with BBU disabled ... Make a static inline wrapper actually static inline. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Sascha Hauer committed on 6 Aug 2018
2018-07-27	7ba0f2d Browse files » ARM: mmu: fix cache flushing when replacing a section with a PTE ... When replacing a section with a PTE, we must make sure that the newly initialized PTE entries are flushed from the cache before changing the entry in the TTB. Otherwise a L1 TLB miss causes the hardware pagetable walker to walk into a PTE with undefined content, causing exactly that behaviour. Move all the necessary cache flushing to arm_create_pte(), to avoid any caller getting this wrong in the future. Fixes: e3e54c644180 (ARM: mmu: Implement on-demand PTE allocation) Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Lucas Stach committed on 27 Jul 2018
2018-07-13	87c08ac Browse files » i.MX: iomuxv3: restore NO_PAD_CTRL semantic ... A NO_PAD_CTRL flag used to keep a pad configuration untouched. With commit 094820a63bfd ("i.MX: iomuxv3: Use helper functions in iomux-v3.h") the NO_PAD_CTRL semantic changed to set a pad configurations to zero, which breaks non-DT boards, where NO_PAD_CTRL is freqently used to keep a boot-up default pad configuration, which often is non zero. Restore the old semantic, dont write PAD_CTRL when NO_PAD_CTRL is set. Signed-off-by: Alexander Kurz <akurz@blala.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Alexander Kurz authored on 10 Jun 2018 Sascha Hauer committed on 13 Jul 2018
2018-07-12	7257e80 Browse files » ARM: MMU: fix arch_remap_range() across section boundaries ... Fixes: e3e54c6441 ARM: mmu: Implement on-demand PTE allocation PGD_FLAGS_WC_V7 lacks the PMD_TYPE_SECT and PMD_SECT_BUFFERABLE flags. Without them a dma_alloc_writecombine() creates an invalid section when it crosses a section boundary. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Sascha Hauer committed on 12 Jul 2018
2018-07-09	49b5c5a Browse files » Merge branch 'for-next/vfxxx' Sascha Hauer committed on 9 Jul 2018
	7ad77a3 Browse files » Merge branch 'for-next/riscv' Sascha Hauer committed on 9 Jul 2018
	6af0422 Browse files » Merge branch 'for-next/misc' Sascha Hauer committed on 9 Jul 2018
	1f3af63 Browse files » Merge branch 'for-next/mips' Sascha Hauer committed on 9 Jul 2018
	64c7203 Browse files » Merge branch 'for-next/kill-oftree-f' ... Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Sascha Hauer committed on 9 Jul 2018
	1073955 Browse files » Merge branch 'for-next/imx8mq' Sascha Hauer committed on 9 Jul 2018
	47d229d Browse files » Merge branch 'for-next/imx' Sascha Hauer committed on 9 Jul 2018
	0d0e894 Browse files » Merge branch 'for-next/dts-warnings' Sascha Hauer committed on 9 Jul 2018