ARM: dts: Add *.dtb.lzo to clean files ...

*.dtb.lzo are generated during compilatiion, delete them.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: ccxmx53: properly guard initcall for multiimage ...

Make sure to not run this board specific initcall on any
other board.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Merge branch 'for-next/socfpga'

Merge branch 'for-next/omap'

Merge branch 'for-next/mtd'

Merge branch 'for-next/mmc'

Merge branch 'for-next/mips'

Merge branch 'for-next/imx'

Merge branch 'for-next/arm'

imx: ocotp: Add code to initialize 'cdev->device_node' ...

In order for cdev_by_device_node() to be able to return approprate
character device for <&ocotp> phandle cdev->device_node needs to be
initialized with dev->device_node. This patche takes care of that

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: pxa: pxa2xx use PSPR for resume address ...

Both lubbock and mainstone suspend to RAM were broken by the same
typo. The linux kernel saves the resume address to PSPR, ie. the scratch
pad register, while it was PSSR which was checked in barebox.

Fixing this typo was tested on mainstone where resume from S3 works.

Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: Remove do_execute and thumb2_execute ...

In commit 104a6a7 support was added
for Thumb2.  It added do_execute() as a way to provide arch dependent
calling veneers for use in "go" and thumb2_execute() as the thumb2 to
arm veneer.

But thumb2_execute() isn't necessary as gcc generates a proper calling
sequence from a standard function pointer call.  Thumb2 barebox is
compiled with the AAPCS ABI which requires this.

It also had a bug and didn't pass the arguments properly, but code
execute via "go" rarely uses arguments so this wasn't very noticeable.

Since thumb2 was always the only user of do_execute(), go ahead and
delete that too.

Signed-off-by: Trent Piepho <tpiepho@kymetacorp.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: Remove kernel booting call for thumb2 mode ...

The asm code to do the actual call into the kernel (or another
barebox) when compiled in thumb2 mode isn't necessary.  gcc generates
a perfectly good calling sequence from a normal function pointer call.
If it didn't, the code in bootstrap_boot() that uses a function
pointer to jump to the 2nd stage barebox from an xloader wouldn't
work.

It appears to be allowed that the call to kernel() could return, as
neither start_linux() nor kernel() are marked noreturn, and there is
code after calls to start_linux().

The asm code has a bug in this case, as it uses bx and not blx, and
thus doesn't set the link register.  Since it's a tail call, this
would be okay, but only if the LR value from the start of
start_linux() (and the callee-saved registers) are restored
beforehand, which isn't done.  The gcc generated call sequence will do
this.

Signed-off-by: Trent Piepho <tpiepho@kymetacorp.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

eukrea-cpuimx35: update defconfig ...

enable chipidea usb driver

Signed-off-by: Florian Vallee <fvallee@eukrea.fr>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

eukrea-cpuimx35: setup usb through chipidea-imx driver ...

OTG and HOST port are tested with a mass storage device.

Signed-off-by: Florian Vallee <fvallee@eukrea.fr>
Signed-off-by: Eric Bénard <eric@eukrea.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

imx35: register usb-misc by default ...

Signed-off-by: Florian Vallee <fvallee@eukrea.fr>
Signed-off-by: Eric Bénard <eric@eukrea.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

video: i.MX IPUv3: Set ldb clocks correctly ...

The clocks for the LVDS display bridge have a fixed /3.5 and a
configurable /1,/2 divider in their path. The configurable divider has
to be explicitly configured for single/dual channel support, so we can't
rely on clock rate parent propagation here. Clear the
CLK_SET_RATE_PARENT flag for the configurable divider and configure the
clock explicitly in the ldb driver.
Tested on a custom i.MX6 board, currently untested on i.MX53.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: mx6sx-sabresdb: set proper hostname ...

Also move the initcall to the level matching the name of the
function.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: mx6sx-sabresdb: drop unneeded makefile rules ...

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

MIPS: import optimized string functions from Linux ...

10x performance gain according to simple test on QEMU malta:
barebox:/ time memcpy 0xa0000000 0xa0001000 0x100000

Signed-off-by: Aleksey Kuleshov <rndfax@yandex.ru>
Acked-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

arm: pxa: Remove pxa_get_nandclk() ...

With a common clock provided for NAND controller, get rid of the
mach/clock.h way of getting the NAND clock.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Robert Jarzmik <robert.jarzmik@free.fr>
Tested-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

arm: pxa: Add clock for Zylonite NFC ...

Add a clock with clk_add_physbase for the NAND flash controller on
Zylonite board.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

arm: pxa: Prepare for NAND clkdev lookup on PXA3xx ...

To allow PXA3xx nand driver to be reused on Marvell Armada 370/XP,
prepare to provide a common clock for the NAND driver on PXA3xx.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Robert Jarzmik <robert.jarzmik@free.fr>
Tested-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

mci: dw_mmc: socfpga: Supply bus-width in platform_data ...

Since there is no OF support in the xloader on socfpga it uses the
platform_data system.  There needs to be a way to supply the
equivalent of the DT property bus-width this way to support devices
that need to use a smaller bus.

So that we don't need to put every flag that might get added to the
MMC_CAP list into platform_data, just put the bus width ones into
platform_data.

The socfpga dts sources specify a bus-width of 4 so use that in the
platform_data for socfpga.

Signed-off-by: Trent Piepho <tpiepho@kymetacorp.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

imx6-mmdc: Fix MAPSR usage ...

The commit ea1fb2f by Eric Nelson
imx6-mmdc: fix automatic power down enable in write level calibration

fixed the incorrect usage of the MAPSR register, but there is one more
place where the MAPSR is misused in the exact same way, so fix that as
well.

Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: Fix bug in remap_range ...

remap_range takes generic MAP_CACHED/MAP_UNCACHED flags which are then
translated into the corresponding ARM specific bits. We call remap_range
internally from dma_alloc_* aswell, but instead of passing the generic
flags we pass the ARM specific bits.
Fix this by creating an internal __remap_range function which takes the
ARM specific bits and use it where appropriate.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: ventana: remove unneeded clock init in DCD ...

The clock driver will overwrite those values anyway, so no
point in setting them in the DCD.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

MIPS: tplink-mr3020: skip pbl lowlevel init if running from RAM ...

TP-Link MR3020 has 4 MiB flash boot ROM.
Usually boot ROM is mapped to 0xbfc00000.
However, as AR9331 allows to remap boot ROM to 0xbf000000
it's better to assume that boot ROM starts at 0xbf000000.

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

MIPS: black-swift: skip pbl lowlevel init if running from RAM ...

Black Swift has 16 MiB flash boot ROM. The standard board's
bootloader (U-Boot_mod) remaps boot ROM to 0xbf000000.

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Tested-by: Yegor Yefremov <yegorslists@googlemail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

MIPS: pbl: add pbl_blt macro ...

Barebox' PBL is able to initialize SoC's memory controller,
but it can be used only if PBL runs from ROM or on-chip SRAM.
MIPS architecture standard boot vector is 0xbfc00000
so on most MIPS SoCs all addresses higher than 0xbfc00000
belong to boot ROM or on-chip SRAM. Thus there's a
simple criterion to check if PBL runs from ROM: just
check if current PC is higher than 0xbfc00000.
Some MIPS boards have ROM start address lower than 0xbfc00000
so it's reasonable to make ROM start address checking board-dependant.

The pbl_blt macro checks if current pc is lower than
the first argument (ROM start address). If so then
next instruction executed is defined by the second argument
of the macro.

Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Tested-by: Yegor Yefremov <yegorslists@googlemail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>