Merge branch 'for-next/misc'

Merge branch 'for-next/mips'

clk: versatile: add basic clocks ...

This adds the necessary basic clocks used on the ARM versatile
platforms.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: add ar9344 clock driver ...

Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

remove checks for xzalloc() returning NULL ...

xzalloc() either returns memory or panics, so checking for NULL is useless.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: imx: cpu: don't store the address of a function parameter ...

The function imx_clk_cpu takes a const char *parent_name as second
paramter. The implementation introduced in commit 9a89ed9d281e then
uses the address of this function parameter to assign clk.parent_names.
This is an address on the stack that is saved in the clk tree and of
course this is easily overwritten by later execution paths of barebox.

Without this fix the clk_dump command reproducibly crashes on i.MX7
(which is the only SoC that makes use of imx_clk_cpu()).

Fixes: 9a89ed9d281e ("clk: imx: Add clk-cpu support")
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>

Merge branch 'for-next/misc'

Merge branch 'for-next/imx'

Merge branch 'for-next/at91'

clk: i.MX7: Remove unused UART clocks array ...

Remove what looks like unused leftover from analogous Linux kernel
code.

Acked-by: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>

clk: clk-fixed-factor: remove leftover debugging ...

Don't spam the output with rate propagation messages. It isn't done
for any other clock.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>

clk: at91: fix clk-main ...

Following warning was reported during boot with
at91sam9263ek with DT enabled.

    "Main crystal frequency not set, using approximate value"

This occured due to a missing parent in clk_rm9200_main.

Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
Cc: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>

i.MX: clk-pllv3: Initially disable PLL_BYPASS bit ...

Commit cbff8031b491 ("i.MX: clk-pllv3: Do not touch PLL_BYPASS bit")
overreached a bit by removing the code that disables the PLL_BYPASS bit
for all architectures instead of making an exception for Vybrid and
i.MX6SL. This causes the USB controller on i.MX6Q to run at bypass
frequency and fail:

    barebox@Boundary Devices i.MX6 Quad Nitrogen6x Board:/ usb
    usb: USB: scanning bus for devices...
    usb: Bus 001 Device 001: ID 0000:0000 EHCI Host Controller
    imx-usb 2184200.usb: port(0) reset error

This patch adds code to unconditionally disable the PLL_BYPASS bit
initially, when the PLL clocks are registered.

Cc: Andrey Smirnov <andrew.smirnov@gmail.com>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Fixes: cbff8031b491 ("i.MX: clk-pllv3: Do not touch PLL_BYPASS bit")
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>

clk: fix clk_get error handling ...

If there is no OFTREE support of_clk_get_by_name failed with
-ENOENT, which caused clk_get to bail out.
This had the effect that nothing was printed on the serial console
with at91sam9263-ek.

There are no error paths that will return -ENODEV as we test for today,
so change this to -ENOENT which is in use.
This allows us to contine with clk_get_sys() in case of other
errors as was the intention of the original fix.

Fixes: 90f7eacb ("clk: let clk_get return errors from of_clk_get_by_name")
Cc: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>

Merge branch 'for-next/mvebu'

Merge branch 'for-next/clk'

i.MX: clk: Remove imx_clk_pllv3_locked() ...

Remove imx_clk_pllv3_locked() which was introduced for the sake of
Vybrid platform. The same effect (waiting on 'locked' bit) can be
achived with vanilla clk_pllv3_enable/disable, which make said
function unnecessary.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

i.MX: clk-pllv3: Do not touch PLL_BYPASS bit ...

Do not touch PLL_BYPASS bit as a part of clk_pll3_enable/disable
execution. For a number of platforms (e.g. Vybrid, i.MX6SL) PLL_BYPASS
is specified as a bit controlling a clock MUX represented by a
dedicated 'struct clk'. Altering that bit as a part of
clk_pll3_enable/disable is equivalent to calling clk_set_parent() and
it makes in the following code:

clk_enable(clk_disable(<some pll>))

change clock chain instead of being a no-op.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk-vf610: Mark all of CCSR muxes with CLK_OPS_PARENT_ENABLE ...

As per VYBRIDRM.pdf, p. 673:

"... When switching clock sources on GL MUX, both active and target
clock sources must be active..."

So mark all of the clock muxes controlled by CCM_CSSR with
CLK_OPS_PARENT_ENABLE to satisfy that requirement. Experiment shows
that failing to do so would result in failure (in some cases CPU
hang).

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: mvebu: Add support for Armada 38x's coreclk ...

This is a mixture of the Armada 370 barebox driver and the Armada 38x Linux
driver.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: let clk_get return errors from of_clk_get_by_name ...

When of_clk_get_by_name fails with -ENODEV it's fine to continue with
clk_get_sys. Other errors (e.g. -EPROBE_DEFER) should be returned however.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: i.MX6ul: Add Clock support for i.MX6ull ...

From linux-4.10 clock support, only skipped some unnecessary clocks

Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Merge branch 'for-next/socfpga'

clk: socfpga: add arria10 clk drivers ...

Arria10 has a (slightly) different clock controller than the
Cyclone5. Add new drivers for it.

This driver only reads out the setup and builds the clocktree,
it does not setup any clocks.

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: socfpga: move driver to subdirectory ...

Prepare for Arria10 clock driver.

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: i.MX50 clock: add clock for USB physbase ...

Add the USB physbase clock entry for i.MX50 SoC to enable USB device
creation via DT.

Signed-off-by: Alexander Kurz <akurz@blala.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Merge branch 'for-next/misc'

Merge branch 'for-next/mips'

clk: clk-gate-shared: fix "no previous prototype" warning ...

The patch fixes these compiler's warnings:

  drivers/clk/clk-gate-shared.c:72:13: warning: no previous prototype for 'clk_gate_shared_alloc' [-Wmissing-prototypes]
   struct clk *clk_gate_shared_alloc(const char *name, const char *parent, const char *companion,
               ^
  drivers/clk/clk-gate-shared.c:89:6: warning: no previous prototype for 'clk_gate_shared_free' [-Wmissing-prototypes]
   void clk_gate_shared_free(struct clk *clk)
        ^

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: No-op CLK_OF_DECLARE if not enabled ...

Instead of wrapping each defenition of CLK_OF_DECLARE hook with
preprocessor guards, change the definition of CLK_OF_DECLARE to expand
into no-op if COMMON_CLK_OF_PROVIDER is not enabled.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>