driver: replace dev_request_mem_region with dev_request_mem_resource ...

dev_request_mem_region doesn't work properly one some SoCs on which
PTR_ERR() values clash with valid return values from dev_request_mem_region.
Replace them with dev_request_mem_resource where possible.

This patch has been generated with the following semantic patch:

// <smpl>
@@
expression d;
expression n;
expression io;
identifier func;
@@
func(...) {
+struct resource *iores;
<+...
-io = dev_request_mem_region(d, n);
-if (IS_ERR(io)) {
+iores = dev_request_mem_resource(d, n);
+if (IS_ERR(iores)) {
...
-	return PTR_ERR(io);
-}
+	return PTR_ERR(iores);
+}
+io = IOMEM(iores->start);
...+>
}

@@
expression d;
expression n;
expression io;
identifier func;
@@
func(...) {
+struct resource *iores;
<+...
-io = dev_request_mem_region(d, n);
-if (IS_ERR(io)) {
+iores = dev_request_mem_resource(d, n);
+if (IS_ERR(iores))
-	return PTR_ERR(io);
-}
+	return PTR_ERR(iores);
+io = IOMEM(iores->start);
...+>
}

@@
expression d;
expression n;
expression io;
identifier func;
@@
func(...) {
+struct resource *iores;
<+...
-io = dev_request_mem_region(d, n);
-if (IS_ERR(io)) {
-	ret = PTR_ERR(io);
+iores = dev_request_mem_resource(d, n);
+if (IS_ERR(iores)) {
+	ret = PTR_ERR(iores);
...
}
+io = IOMEM(iores->start);
...+>
}

@@
expression d;
expression n;
expression io;
identifier func;
@@
func(...) {
+struct resource *iores;
<+...
-io = dev_request_mem_region(d, n);
+iores = dev_request_mem_resource(d, n);
+if (IS_ERR(iores))
+	return PTR_ERR(iores);
+io = IOMEM(iores->start);
...+>
}

@@
identifier func;
@@
func(...) {
<+...
struct resource *iores;
-struct resource *iores;
...+>
}
// </smpl>

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: tegra: don't enable UART clocks by default ...

Now that we are registering a proper driver for the
UARTs we no longer need to enable the clocks unconditionally.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: tegra: slow down MSELECT to 102MHz ...

Don't know where I got the 204MHZ previously, but
102MHz is the official supported maximum.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: tegra124: add PCIe clocks ...

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: tegra124: add PLLE setup functions ...

This adds functions to bring up the new style
Tegra114+ PLL_E.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: tegra30: add PCIe clocks ...

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: tegra: add PLLE setup functions ...

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

resource: Let dev_request_mem_region return an error pointer ...

For all users fix or add the error check.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: tegra: add Tegra124 driver ...

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: tegra: don't bug out on zero PLL postdiv ...

As the real value is 2^p a input value of 0 is
actually valid.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: tegra: allow variable sized muxes ...

Tegra124 extended the mux by 1bit to allow for
more PLL sources.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: tegra20: register i2c clocks ...

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: tegra30: register i2c clocks ...

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: tegra: allow to register clocks with 16 bit divider ...

Some peripherals have a double wide divider in front
of them.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: tegra: remove device reset hack ...

Now that we have a proper reset controller, it
isn't necessary anymore to keep the device reset
hack coupled to the clock.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: tegra: reset UARTS from clock controller ...

The console devices are the only ones that can't
use the reset controller properly, as they get
registered from platform code. Reset those devices
from the clock controller.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

reset: add tegra reset controller ...

Allows us to drop the hack in the clock controller
and implement proper reset at device level.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Merge branch 'for-next/tegra' ...

Conflicts:
	arch/arm/dts/tegra20-colibri.dtsi
	arch/arm/dts/tegra20-paz00.dts
	arch/arm/dts/tegra20.dtsi
	drivers/clk/tegra/clk-periph.c

clk: gate: add flags argument to clock gate constructor ...

This adds a clk_gate_flags argument to clock gate creation functions
to allow the introduction of new clock gate modifiers.

Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: tegra: add Tegra3 driver ...

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: tegra: consider new T30 clock registers ...

Tegra3 has some new clocks and resets. The new
registers don't form a linear range with the
old ones.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: tegra20: convert to dt-binding defines ...

Allows to make relationship between DT and driver
more explicit and avoids duplication.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: clk-fixed-factor: pass flags to initializers ...

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: clk-gate: pass flags to initializers ...

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: clk-mux: pass clk flags from initializers ...

struct clk has a flags field, let the clk-mux initializers set this
field.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: tegra: add SDMMC clocks ...

Provide peripheral clocks for the SD controller.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

tegra: speed up system bus ...

We run the system bus from the OSC clock during init, to avoid crashing
the system while reconfiguring the PLLs.
Switch to a more reasonable clock when we are done with this.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

tegra: add peripheral clocks ...

Only UART clocks are included for now, but the code should cover
other peripherals needs, too.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

tegra: add new clock framework driver ...

This removes the existing Tegra CAR driver and replaces it with code
ported from the Linux clock framework.

In the current state only the relevant PLLs are supported, but this is
no functional regression from the existing code.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>