Merge branch 'for-next/zii'

Merge branch 'for-next/stm32'

Merge branch 'for-next/mvebu'

ARM: dts: imx6ul: phycore: Add phyCORE-i.MX 6ULL with eMMC ...

Add a phyCORE-i.MX 6ULL with eMMC. It has following features:
	- i.MX 6ULL Y2 792 MHz
	- 512 MB RAM
	- 4 GB eMMC
	- 10/100 MBits Ethernet
	- USB OTG
	- USB Host

Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: imx6ul: phycore: Prepare for eMMC module ...

Prepare for the new phyCORE-i.MX 6UL/ULL eMMC module by extending the
dts filenames by their boot medium. Also add the boot medium to the
compatible to be able to perform boot medium dependent setup code.

Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: phytec-som-imx6: Add low cost variant for imx6dl phycore ...

The phyCORE-i.MX 6Solo/DualLight is available with low-cost and
full-featured phyBOARD-Mira. One crucial difference is the supported
max. ethernet speed. On the full-featured Mira it is 1000 MBit/s but on
the low-cost Mira it is only 100 MBit/s. To cover this difference two
different images are necessary for low-cost and full-featured. Thus a
low-cost variant is added for the phyCORE-i.MX 6Solo with NAND and the
phyCORE-i.MX 6 DualLight with eMMC.

Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: Rename zii-imx7d-rpu2 to zii-imx7d-dev ...

To prepare for addition of another ZII i.MX7D based board, i.MX7D
RMU2, rename zii-imx7d-rpu2 to zii-imx7d-dev to avoid any image naming
confusion.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: stm32mp: add entry point, not point.pblb to pblb-y ...

Other images/Makefile.${arch}s, e.g. images/Makefile.imx, populate
pblp-* with the entry points to build, not the pbl file that's
generated. Adjust the images/Makefile.stm32mp  to do the same.

Cc: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: stm32mp1: rename to stm32mp ...

Serial and clk driver both depend on CONFIG_ARCH_STM32MP1,
so either the Kconfig symbol or their depend needs to change.

Patches posted by the vendor to Linux, U-Boot and their BSP
Yocto-Layer speak of a STM32MP-Family of which the STM32MP1
is the first series, thus rename the arch by dropping the 1.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

images/mvebu: use space before = instead of tab ...

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

images/mvebu: Convert Armada machines to mvebuimg ...

The results are bytewise identical apart from armada-xp-db where the
(AFAIK unused) parameters for the binary header are different (i.e.
0000005b 00000000 instead of 0000005b 00000068 for all other boards).

The advantage is that the build system now knows about the binary
headers and changes to them result in a rebuild of the images.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Merge branch 'for-next/misc'

images: ignore *.csfbin files ...

The csfbin files are created during a HABV4 build, ignore them since they
are automatically generated.

Signed-off-by: Rouven Czerwinski <r.czerwinski@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

images: remove forgotten occurences of *.imx-sram-img ...

Starting with commit 5a1a5ed2537d ("ARM: images: use piggydata") this file type
is not known anymore, so clean up.

Signed-off-by: Ulrich Ölmann <u.oelmann@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: i.MX6: add support for Digi CCIMX6UL SBC Pro ...

Add support for the Digi CCIMX6UL SBC Pro.
It is based on the Digi CCIMX6UL SOM with 256MB RAM and 256MB NAND
flash.

v2:
- fix includes
- rename folder to som
- switch to compressed dtb
- remove the unnecessary get_runtime_offset
all from Ahmad Fatoum

Signed-off-by: Rouven Czerwinski <r.czerwinski@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Merge branch 'for-next/mvebu'

ARM: Layerscape: TQMLS1046a: Support booting from QSPI ...

We have to build correct images suitable for QSPI, thus have to call
lspbl_spi_image instead of lspbl_image. In lowlevel code call the
xload function which detects the bootsource rather than hardcoding
SD/MMC.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: Layerscape: TQMLS1046a: unify pbi files ...

This unifies the two different pbi files. With our approach for QSPI
booting differences in the pbi files are not necessary:

- We do not do execute in place for QSPI, so we do not need different
  image execution addresses
- Setting up the QSPI clock doesn't hurt even for SD boot

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: Layerscape: Add QSPI boot support ...

Booting Layerscape from QSPI is a bit tricky and the approach we take is
different from the one U-Boot has taken, so it's worth writing and
reading the following explanation.

The QSPI controller can map the Flash contents into the memory space (On
LS1046a at 0x40000000). The PBL unit uses this to read the RCW from this
memory window. The Layerscape SoCs have a PowerPC history, so it seemed
appropriate for the designers to let the QSPI controller operate in
big endian mode by default. To let the SoC see the correct RCW we have
to write the RCW and PBI data with be64 endianess. Our PBL image tool
pokes the initial binary into the SoC internal SRAM using PBI data as
done with SD/MMC boot aswell. barebox then changes the QSPI controller
endianess to le64 to properly read the barebox binary (placed at an
flash offset of 128KiB, so found in memory at 0x40020000) into SDRAM and
jumps to it.

U-Boot has another approach. Here the initial binary is executed in
place directly at 0x40100000. This means the QSPI controller endianess
must be swapped inside the PBI data. This has the effect that the whole
RCW/PBI data must be 64bit endianess swapped *except* the very last word
of the PBI data which contains the CRC command and is read already with
changed endianess. As a conclusion when porting QSPI PBI files from U-Boot
to barebox skip commands changing the endianess in the QSPI controller
and make sure the image is executed in internal SRAM and not in the
Flash memory window.

Lines like this should be removed:

09550000 000f400c

This sets the binary execution address:

09570604 40100000

For barebox it should be changed to 0x10000000.

As a result the PBI files can probably be unified between SD and QSPI
boot.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: Layerscape: TQMLS1046a: Unify SD and eMMC images ...

TQ has unified SD and eMMC images in their U-Boot. Do the same in
barebox aswell.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

arm: add basic support for the Armada XP DB platform ...

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Merge branch 'for-next/stm32'

Merge branch 'for-next/layerscape'

ARM: Makefile.imx: group and sort board entries ...

Add new grouping comments for vf6xx- and Cortex-A7 based i.MX6 boards.
Sort moved entries alphabetically.

Signed-off-by: Alexander Kurz <akurz@blala.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: Layerscape: Add TQ TQMLS1046a board support ...

This adds support for the TQ TQMLS1046a board. Currently supported:

- UART
- SD/MMC
- Network on eth3, eth2 currently not working for unknown reasons

First stage support exists but is currently untested. Serdes ports are
not yet supported.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: Layerscape: Add LS1046a RDB board support ...

The RDB is the Freescale LS1046a reference board. This patch adds
support for it. Currently supported:

- DDR4 RAM as read from SPD EEPROM
- UART
- SD/MMC
- RGMII network ports

The Serdes ports are currently not supported.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: Add basic Layerscape support ...

This adds basic Layerscape support:

- Makefile/Kconfig
- Register maps
- errata workarounds

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

pbl multiimage: Allow to check image sizes ...

PBL images are often constrained in size by limitations exposed by
the SoCs SRAM size or partition sizes on the boot device. So far
we tried to configure these limits in Kconfig, but with PBL multi
images and thus different limitations for the different supported
images this no longer works. This patch has another approach for
it:

During build time make variables containing the relevant sizes for
each image are created. These are:

PBL_CODE_SIZE_$(symbol)
PBL_MEMORY_SIZE_$(symbol)
PBL_IMAGE_SIZE_$(symbol)

PBL_CODE_SIZE_$(symbol) contains the pure code size of the PBL, it
should be smaller than the available SRAM during boot. Normally the
PBL's bss segment also needs to be in the initial SRAM, for this
case PBL_MEMORY_SIZE_$(symbol) is the relevant variable.
PBL_IMAGE_SIZE_$(symbol) contains the full size of the PBL image
including the compressed payload (but without any image headers
created later by SoC specific image tools).

$(symbol) is a placeholder for the start symbol used for this PBL image,
thus for the i.MX53 QSB with entry start_imx53_loco

PBL_CODE_SIZE_start_imx53_loco

will be created. The images/Makefile.* can use these variables directly
to check sizes or specify the same variables with a "MAX_" prefix. So
when images/Makefile.imx specifies

MAX_PBL_CODE_SIZE_start_imx53_loco = 0x10000

then the build system will make sure that the PBL code for the QSB will
not get bigger than 64KiB.

Also included in this patch are the size restrictions for the i.MX8MQ
images as an example how to use this.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: Add initial STM32MP1 support ...

This adds initial STMicroelectronics MP1 support along with support
for the DK2 devel board. Only very basic support:

- UART
- SDRAM memory base/size
- No 1st stage support

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Merge branch 'for-next/rpi'