ARM: pbl: keep __image_end section ...

Not all architectures are referencing the image_end section from
code, in which case the linker is free to drop the section, which
then messes up the calculation of the _barebox_image_size linker
variable.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: zii-commmon: Fix NULL pointer dereference in do_rdu1_switch_reset() ...

We need to go to parent's private data to get a pointer to struct
rave_sp. Fix that.

Fixes: 493e2ee38f ("ARM: zii-common: add support for switch reset on RDU1")
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: at91: build for all SoCs when AT91_MULTI_BOARDS is selected ...

This reverts a hunk I missed after a rebase:
A previous commit restricts ARCH_BAREBOX_MAX_BARE_INIT to only
non-multi-image boards, so no need to touch it to be compatible
with the new multi-image changes.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Merge branch 'for-next/rsa'

Merge branch 'for-next/mxs'

Merge branch 'for-next/misc'

Merge branch 'for-next/layerscape'

Merge branch 'for-next/imx'

Merge branch 'for-next/bfin'

Merge branch 'for-next/at91'

Merge branch 'for-next/arm'

ARM: stm32mp: dk2: rename function according to init level ...

dk2_postcore_init is not at postcore init level like the name would
suggest, but at mem init level. Rename it accordingly.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: dts: stm32mp: add barebox-enviroment on DK boards ...

Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: at91: add basic sama5d2-som1-ek1 support ...

The ATSAMA5D27-SOM1-EK1 is Microchip's evaluation kit for the SAMA5D2
System in Packages (SiPs). The ATSAMA5D27C-D1G-CU SIP embeds 128 MB
of DDR2 DRAM and the SoM has a PMIC, QSPI flash and a 100Mbps PHY.

barebox already supports the sama5d2 clocks, GPIO/Pinctrl, QSPI
controller and Ethernet MAC. Most notable omission is the sama5d2
variant of the SDHCI, which differs from the MCI used by previous AT91
boards, but we kernel boot over the network works, so lets add the board
now and have the SDHCI follow later.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: at91: add basic sama5d2 support ...

Add hardware description, chip identification and clock changes to
support the sama5d2 SoC.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: at91: microchip-ksz9477-evb: add debug_ll UART ...

The EVB has the dbgu TX on PB31. Pinmux and set up the UART on it when
DEBUG_LL is enabled, so early barebox boot messages can be printed.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: at91: import lowlevel dbgu UART init code from at91bootstrap ...

For use in PBL, import dbgu init code from:
https://github.com/linux4sam/at91bootstrap/blob/v3.8.12/driver/at91_usart.c

The brgr calculation at the beginning is a untangled version
of the BAUDRATE macro from the usart.h header:

	#define BAUDRATE(mck, baud) \
		(((((mck) * 10) / ((baud) * 16)) % 10) >= 5) ? \
		(mck / (baud * 16) + 1) : ((mck) / (baud * 16))

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: at91: import lowlevel clock initialization from at91bootstrap ...

For use by future at91 first stage bootloaders, this commit imports
https://github.com/linux4sam/at91bootstrap/blob/v3.8.12/driver/pmc.c

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: at91: use compressed DTB for AT91_MULTI_BOARDS ...

To offset the size increase by using multi-image have the DTBs be
compressed. This reduces e.g. the microchip_ksz9477_evb_defconfig
by about 22K from 244K to 222K.
This will also come in handy when implementing first stage support
later on.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: at91: build for all SoCs when AT91_MULTI_BOARDS is selected ...

With the addition of 15afd9d25 ("ARM: at91: Add initial support for the
EVB-KSZ9477 eval board"), we now have two multi-image capable boards
supported, but users still have to choose a specific SoC, so they can't
be selected at the same time.

Fix this, by restricting the menu to the non-multi-image configurations,
i.e. CONFIG_ARCH_* symbols become specific to non-multi-image.

The multi-image configurations on the other hand directly select the
CONFIG_SOC_* symbol they require. Existing CONFIG_ARCH_* usage is
adjusted to align with the new usage.

Eventually, we would want to have a at91_multi_defconfig along with
this, but for now leave existing configs as is.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: at91: don't define ARCH_BAREBOX_MAX_BARE_INIT_SIZE for multi-image ...

Since ed04a7c3 ("pbl multiimage: Allow to check image sizes"), we can
now check sizes per entry point, so no need to a Kconfig symbol that
applies to all boards for that. Thus drop the Kconfig symbol for
multi-image, so per-entry-point max image sizes can follow in future.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: at91: delete no-longer needed #ifdef guards ...

c16bcbc644 ("ARM: at91: remove unused defines") removed conflicting
definitions from the headers, so we can include the headers
and code that uses them unconditionally now.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: at91: at91sam9x5ek: squelch new dtc warning ...

Since v1.5.0, dtc has been applying a heuristic to detect spi busses. It
erroneously thinks the spi node in at91sam9x5ek.dts defines a spi bus:

  ./arch/arm/dts/at91sam9x5ek.dts:25.9-29.7: Warning (spi_bus_bridge):
  	/ahb/apb/pinctrl@fffff400/spi: incorrect #address-cells for SPI bus
  ./arch/arm/dts/at91sam9x5ek.dts:25.9-29.7: Warning (spi_bus_bridge):
  	/ahb/apb/pinctrl@fffff400/spi: incorrect #size-cells for SPI bus
  ./arch/arm/dts/at91sam9x5ek.dtb: Warning (spi_bus_reg):
  	Failed prerequisite 'spi_bus_bridge'

Avoid this by renaming the node. While at it move the node to top-level
to reduce indentation.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: mmu: use client domain permissions to support ARMv7 eXecute Never ...

The ARM Architecture Reference Manual notes[1]:
> When using the Short-descriptor translation table format, the XN
> attribute is not checked for domains marked as Manager.
> Therefore, the system must not include read-sensitive memory in
> domains marked as Manager, because the XN bit does not prevent
> speculative fetches from a Manager domain.

To avoid speculative access to read-sensitive memory-mapped peripherals
on ARMv7, let's use client domain permissions for all memory, so the XN
bit (and also R/W bits) can function.
This aligns us with what Linux is doing on ARMv7.

This fixes cache corruption instances that had been observed on the
i.MX6UL(L) when the instruction prefetcher speculates into memory following
the end of a 512M SDRAM[2].

While this is not necessary to avoid speculative accesses on < ARMv7,
we could probably have everything there in client domain as well, but
due to lack of test coverage, we'll restrict the change to ARMv7.

[1]: B3.7.2 - Execute-never restrictions on instruction fetching
[2]: "Cache Corruption on MX6UL(L)": https://community.nxp.com/thread/511925

Fixes: 0198567c4 ("ARM: mmu: mark uncached regions as eXecute never on v7")
Signed-off-by: Ahmad Fatoum <ahmad@a3f.at>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: mmu: set R/W bits in ARMv7 translation table ...

With barebox using the manager permissions for domain 0 that's used for
all page table entries and directories, we never had the need so far to
explicitly set R/W bits. We did so anyway for sections in the early MMU
code, but later on in the normal MMU setup, we didn't do so consistently.

In preparation for switching to DOMAIN_CLIENT for ARMv7, configure R/W
everywhere in normal MMU code as well.

Signed-off-by: Ahmad Fatoum <ahmad@a3f.at>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: cache-armv7: remove duplicate domain initialization ...

We already call set_domain each time we do __mmu_cache_on. Writing the
DACR in the armv7 __mmu_cache_on is thus superfluous. Drop it.

This changes existing behavior, whereas all 16 memory domains had the same
access permissions set (manager) before, now only the first domain has.
This is ok, as we only ever use domain 0 in barebox and on non-armv7,
we don't bother with the other ones at all.

Signed-off-by: Ahmad Fatoum <ahmad@a3f.at>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: cache-armv7: remove superfluous instruction ...

There are two tst r11, #0xf with nothing in between them that changes
r11. This a left over from the kernel code that checks for VMSA twice,
once to check if the page table should be setup and once to more to
flush the TLB. We do the setup in the caller already, so the tst serves
no useful purpose. Delete one.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: mmu: remove no longer accurate comment ...

This comment refers to the state of things prior to e3e54c644
("ARM: mmu: Implement on-demand PTE allocation"). Since then, we no
longer generate 2nd level page tables directly below. Remove it
to avoid confusion.

Cc: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: use system.h's get_cr() for cpuinfo ...

Instead of open-coding the get_cr(), use the already available helper
in <asm/system.h> same as we do for 64-bit ARMv8.
The only difference is that the "memory" clobber is replaced by "cc".
This is ok as we don't expect get_cr() to affect memory and because
we do it elsewhere in barebox without a "memory" clobber already.

While at it, move it out the #if/#else clause as the helper changes
behavior depending on the same CONFIG option anyway.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: stm32mp: add bootm handler for images ...

STM32 images are preceded by a fixed-size 256 byte header, which is
interpreted by the TF-A first stage bootloader and isn't executable
as ARM code.

To maintain the ability to network boot them, add a bootm handler that
skips the header.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>