RISC-V: unbreak built-in dtb ...

The commit c5d38e92010174 ("lds: Add and use RO_DATA_SECTION macro")
consolidates all RO sections link script declaration in the single
RO_DATA_SECTION macro. So all all individual RO section declarations
have to be removed from per-arch linker scripts.

Alas the BAREBOX_CLK_TABLE and the BAREBOX_DTB link script sections
were not removed from RISC-V linker script making these sections
declared twice. As a result incorrect __clk_of_table_start and
__dtb_start addresses are passed to the barebox code therefore
the RISC-V barebox is completely unusable.

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

MIPS: don't overlay relocation data with BSS ...

.bss __rel_start (OVERLAY) was used to optimize RAM size used by
barebox. Since .bss and __rel_start overlap, we should clear bss only
after __rel_start was used. Following patch changed initialization
sequence to clear .bss before __rel_start:
1e5aef61fc6a444 ("MIPS: reloc: init bss and cpu")

This make relocation buffer unusable and broke relocation with different
symptoms reported by Antony Pavlov <antonynpavlov@gmail.com>:
  * iomem output has no information on sdram regions, so memtest is unusable;
  * pc = 0xa081232c, relocation does not work, barebox is located with 8M offset
    from start of RAM. The board has 256M and relocation routine
    should move barebox code much higher;
  * pc = 0xa081232c, so barebox code works from KSEG1 not from KSEG0 as MMU=y option implies.

There is a choice of moving .bss clear sequence after __rel_start or
remove this optimization. Since the use of this optimization is minimal
and danger to trap in to similar issue is still high, i prefer to remove
this optimization.

As result of this change, we need to fix calculation of relocation are
size:
relocate_code() calculates relocation area size as a sum (barebox_image_size +
bss_len). barebox_image_size and bss_len are calculated as (__image_end -
__image_start) and (__bss_stop - __bss_start) respectively. This doesn't take
into account relocation data placed between  __image_end and __bss_start.
However relocation preserves BSS position relative to image start, as if
relocation data is still there. This causes RAM overflow during BSS
initialization in main_entry(). This problem may be hidden due to the alignment
of the `relocaddr`.

Reported-by: Antony Pavlov <antonynpavlov@gmail.com>
Fixes: 1e5aef61fc6a444 ("MIPS: reloc: init bss and cpu")
Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Signed-off-by: Peter Mamonov <pmamonov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: imx6: properly check for IPU presence ...

Since a73850bd76d0 (ARM: imx: disable IPU QoS setup for correct SoCs), which
fixed the condition to not execute the IPU QoS fixups on SoCs that don't have
a IPU, the fixups aren't applied on i.MX6Q/DP anymore, since those SoCs were
missing from the whitelist.

Add a function to make it a bit more clearer what we are checking here and add
the Q/DP SoCs.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

MIPS: actually use CONFIG_MIPS_RELOCATION_TABLE_SIZE ...

The commit 28ed10d6a67c9 ("MIPS: relocation: add relocation support")
introduce the Kconfig CONFIG_MIPS_RELOCATION_TABLE_SIZE parameter
but it is never used.

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: qemu-virt64: convert to assembly entry ...

The C entry function isn't naked, so tries to push to the stack
in the function prologue. This doesn't work on QEMU where there
is no valid SP on entry. Convert the lowlevel entry to the
assembly facilities provided for this case.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Merge branch 'for-next/zynq'

Merge branch 'for-next/rpi'

Merge branch 'for-next/misc'

Merge branch 'for-next/layerscape'

Merge branch 'for-next/imx'

MIPS: dts: rename tplink-mr3020.dts -> ar9331_tl_mr3020.dts ...

Linux MIPS uses <soc-name>_<board-name>.dts board dts-file
naming scheme so use it in barebox too.

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: zynq: zedboard: add PBL console support ...

Allows for significantly easier debugging of PBL functions.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: zynq: zed: partially revert zynq_cpu_lowlevel_init() chnages ...

Calling arm_cpu_lowlevel_init() from zynq_cpu_lowlevel_init() adds a stack
push/pop to the latter function which doesn't work this early in the boot.

As the BootROM apparently hands proccessor control to us in abort(!?!)
mode, setting up a stack requires duplicating most of arm_cpu_lowlevel_init().
To get around this catch-22 move the call to arm_cpu_lowlevel_init back into
the board lowlevel start function, so we don't need a stack at all.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: Layerscape: setup icids for the IOMMU ...

The Isolation Context Identifiers (icid) have to be configured in the
hardware and communicated to the Kernel via device tree fixups. This
adds the missing bits and pieces to make the IOMMU work under Linux.

As of Linux-5.5 the SMMU doesn't work out of the box. This series has
been tested in conjunction with this Kernel series:
https://lore.kernel.org/patchwork/cover/997994/

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

include/soc/fsl: Make struct ccsr_qman v3 specific ...

struct ccsr_qman is ifdeffed for different versions of this structure.
CONFIG_SYS_FSL_QMAN_V3 is not defined which means we happen to use
the wrong version on LS1046a. Hardcode it to the v3 version to make
it work on LS1046a and rename it to ccsr_qman_v3 to make it obvious
that it needs a change on non v3 versions.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: Layerscape: replace overcomplicated macros ...

The icid tables are generated with several macros which makes the code
hard to read. Drop the macros.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

esdhc-pbl: remove now unused imx8_esdhc_load_piggy ...

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: nxp-imx8mq-evk: fix second stage booting ...

If the whole image already resides in DRAM, e.g. by starting the
image via the bootm handler we try to load the piggydata from storage,
which may well be different from our expected piggydata, already
present in DRAM.

Fix this by avoiding the special piggydata load function, but instead
load the whole image after DRAM is up and just replace the PBL part to
ensure we are still running the HAB validated code after TF-A hands
back control to our code in DRAM.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

esdhc-pbl: allow to skip starting i.MX8 image ...

Add an option that allows to just load the image into memory, but
return to the calling function instead of directly jumping to the
loaded image.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: zynq: zed: use zynq_cpu_lowlevel_init() ...

Make sure the required workarounds for CPU errata are applied.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: zynq: add Zynq specific lowlevel CPU init function ...

This adds a Zynq specific CPU lowlevel init function, which applies
the required workarounds for the Cortex A9 r3p0 core.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: rpi_defconfig: Enable more features ...

This enabled more features for the rasperrypi boards:

- DWC2 USB driver
- Networking support
- GPIO EXP driver
- LED support
- more commands

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: rpi mailbox: Use non interruptible timeout ...

This makes sure that during a mailbox transfer no other mailbox transfer
is started. This happens on a raspberrypi3 where one GPIO on the
firmware GPIO controller (which is controlled via mailbox) is registered
as a heartbeat LED. With this it can happen that during a mailbox
transfer the poller which drives the heartbeat LED is triggered in
is_timeout() which results in corrupted transfers.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: rpi_defconfig: Enable raspberry GPIO exp driver ...

Enable the recently introduced GPIO exp driver.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: bcm2835 mbox: use pr_* to print messages ...

To give the user an idea where the messages come from.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

gpio: Add raspberrypi exp gpio driver ...

Taken from the kernel adopted to barebox.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: bcm2835 mbox: Remove response valid check ...

Not all messages return a valid response as they do not send a response
at all. This is at least true for the SET_GPIO_STATE and SET_GPIO_CONFIG
messages.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

MIPS: loongson: rename CPU_LOONGSON1 to CPU_GS232 ...

The CPU in the loongson 1b SoC is called GS232.
Here is some active chips and it's core:

NAME              CPU       Core(s)
The loongson 3 series/server & desktop
  3A3000/3B3000     GS464E    64bit x4
  3A2000/3B2000     GS464E    64bit x4
  3B1500            GS464     64bit x8
  3A1000            GS464     64bit x4

The loongson 2 series/low power
  2K1000            GS264     64bit x2
  2F                GS464     64bit x1
  2H                GS464     64bit x1

The loongson 1 series/embeded
  1C101             GS132R    32bit ?
  1D                GS132     32bit ?
  1C                GS232     32bit x1
  1B                GS232     32bit x1
  1A                GS232     32bit x1

see:
[1] http://www.loongson.cn/product/

Signed-off-by: Du Huanpeng <duhuanpeng@loongson.cn>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: nxp-imx8mq-evk: fix bootflow comment ...

The comment above nxp_imx8mq_evk_start is no longer accurate, as there
is no trampoline in DRAM anymore. Change the comment to reflect the current
boot flow.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: nxp-imx8mq-evk: clean up nxp_imx8mq_evk_start ...

Mostly cosmetic changes:
- reduce scope of local variabes
- wrap comment to fir 80 char limit
- check return value from imx8_esdhc_load_piggy
- drop intermediate function that only wraps a single other function

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>