clk: zynq: add QSPI reference clock ...

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Merge branch 'for-next/zynq'

clk: i.MX6ul: Disable GPMI_IO clk before reparenting ...

Before reparenting the ENFC_SEL mux we have to make sure the GPMI_IO clk
is disabled as recommended in the reference manual. Otherwise glitches
may occur on the GPMI clk which result in a later NAND failure:

MXS: Timeout resetting block via register 0x01806000
mxs_nand 1806000.gpmi-nand@1806000.of: probe failed: Connection timed out

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: zynq: remove clkdevs ...

They aren't needed anymore, as all the Zynq devices now
use a DT based clock lookup.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: zynq: partially sync with Linux ...

Sync the clock enum with the clocks used by Linux and the DT binding.
Implement AMBA bus clocks and SPI and SDIO peripheral clocks and
register a DT clock controller, so the clocks can be looked up by
DT handle.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: zynq: fix up address from DT ...

The upstream Zynq 7000 DT describes the SLCR child devices physical
address as an offset within the SLCR. The driver thus needs to add
the SLCR base offset to the address before trying to map the MMIO
region.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: zynq: improve PLL enable handling ...

Ensure that both the powerdown and reset bits are cleared when the PLL
gets enabled, as any of those set would prevent the PLL from working.

Also add a status readback function, so the real status of the PLL is
reflected in the Barebox clock state.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: zynq: use base address of clock controller ...

The clock controller is a subregion of the SLCR, use the real base
of this region for mapping the registers. This will allow to switch
to DT based probing later.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: zynq: move clock controller driver to drivers/clk ...

No functional change, just adjusting the Zynq code to common practise.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: i.MX6qp: Fix location of the enfc_sel mux ...

On the i.MX6qp the enfc_sel mux is at bits 15-17, not on 16-17. Fix
this. During clock tree initialization we reparented the enfc_sel to:

	clk_set_parent(clks[IMX6QDL_CLK_ENFC_SEL], clks[IMX6QDL_CLK_PLL2_PFD2_396M]);

This resulted in a register setting 0b110 for the enfc_sel mux which is
reserved. Apparently this reserved setting resulted in the enfc clock
being driven from pll3_pfd3_454m. This means our enfc clock was the
factor 454/396 too high.

With b534f79112f0 ("clk: imx6: Fix procedure to switch the parent of
LDB_DI_CLK") we happened to disable pll3_pfd3_454m during init, so with
this commit NAND stopped working entirely on i.MX6qp.

Both issues are fixed with this patch

Fixes: b534f79112f0 ("clk: imx6: Fix procedure to switch the parent of LDB_DI_CLK")
Fixes: 92fd61d12723 ("clk: i.MX6: Fix enfc_sel for i.MX6dqp")

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: zynqmp: rename driver specific CLK_MUX_READ_ONLY ...

Since commit c7cc27d006cc (clk: mux: Support CLK_MUX_READ_ONLY flag)
Barebox defines the CLK_MUX_READ_ONLY flag like Linux.

The ZynqMP clock driver used the flag before, because this flag is used
to convey this information from the PMU firmware to the Linux driver.
However, the flags of the common clock framework and the flag of the
protocol between PMU firmware and the ZynqMP clock driver should be
handled separately.

Therefore, add a driver specific prefix to the flag definition in the
ZynqMP driver.

Fixes the warning

	drivers/clk/zynqmp/clk-mux-zynqmp.c:18:0: warning: "CLK_MUX_READ_ONLY" redefined
	In file included from drivers/clk/zynqmp/clk-mux-zynqmp.c:13:0:
	include/linux/clk.h:350:0: note: this is the location of the previous definition

Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: imx6: define an enum for ldb mux inputs ...

For better readability should this code be reviewed
in future, replace the hardcoded input numbers
with an enum.

This is just a cosmetic change and was verified
to not affect clk-imx6.o.

Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Tested-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: imx6: Fix procedure to switch the parent of LDB_DI_CLK ...

Due to incorrect placement of the clock gate cell in the ldb_di[x]_clk
tree, the glitchy parent mux of ldb_di[x]_clk can cause a glitch to
enter the ldb_di_ipu_div divider. If the divider gets locked up, no
ldb_di[x]_clk is generated, and the LVDS display will hang when the
ipu_di_clk is sourced from ldb_di_clk.

To fix the problem, both the new and current parent of the ldb_di_clk
should be disabled before the switch. This patch ensures that correct
steps are followed when ldb_di_clk parent is switched in the beginning
of boot. The glitchy muxes are then registered as read-only. The clock
parent can be selected using the assigned-clocks and
assigned-clock-parents properties of the ccm device tree node:

        &clks {
                assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
                                  <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
                assigned-clock-parents = <&clks IMX6QDL_CLK_MMDC_CH1_AXI>,
                                         <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>;
        };

The issue is explained in detail in EB821 ("LDB Clock Switch Procedure &
i.MX6 Asynchronous Clock Switching Guidelines") [1].

[1] http://www.nxp.com/files/32bit/doc/eng_bulletin/EB821.pdf

Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@nxp.com>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Akshay Bhat <akshay.bhat@timesys.com>
Tested-by Joshua Clayton <stillcompiling@gmail.com>
Tested-by: Charles Kang <Charles.Kang@advantech.com.tw>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
[afa: reviewed for barebox]
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Tested-by: Andrey Smirnov <andrew.smirnov@gmail.com>
[afa: ported to barebox from Linux commit 5d283b0838]
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: imx6: Make the LDB_DI0 and LDB_DI1 clocks read-only ...

Based on Kernel commit 03d576f202 ("clk: imx6: Make the LDB_DI0 and LDB_DI1 clocks read-only"):

| Due to incorrect placement of the clock gate cell in the ldb_di[x]_clk
| tree, the glitchy parent mux of ldb_di[x]_clk can cause a glitch to
| enter the ldb_di_ipu_div divider. If the divider gets locked up, no
| ldb_di[x]_clk is generated, and the LVDS display will hang when the
| ipu_di_clk is sourced from ldb_di_clk.
|
| To fix the problem, both the new and current parent of the ldb_di_clk
| should be disabled before the switch. As this can not be guaranteed by
| the clock framework during runtime, make the ldb_di[x]_sel muxes read-only.
| A workaround to set the muxes once during boot could be added to the
| kernel or bootloader.
|
| Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
| Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
| Signed-off-by: Shawn Guo <shawnguo@kernel.org>

[afa: reviewed for barebox]
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Tested-by: Andrey Smirnov <andrew.smirnov@gmail.com>
[afa: ported from Linux kernel commit 03d576f202]
[afa: added exception for i.MX6QP, see kernel commit f4a0a6c309]
[afa: added cpu_has_err009219 helper function]
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: imx6: remove quirky clk_set_parent(LDB_diN_sel, pll5_video_div) ...

barebox has inherited the clk_set_parent(ldb_diN_sel, pll5_video_div)
from upstream kernel commit 32f3b8da22 ("ARM i.MX6q: set the LDB serial
clock parent to the video PLL"), where it was enabled for all i.MX6Q
revisions after 1.0. It was applied whenever CONFIG_DRIVER_VIDEO_IMX_IPUV3
was defined.

The kernel removed this reparenting again as a preventive measure
against ERR009219 in 03d576f202 ("clk: imx6: Make the LDB_DI0 and
LDB_DI1 clocks read-only").

In barebox, the reparenting remains and is done for all i.MX6 SoCs
with a revision > 1.0. On all of them, except for the QuadPlus and
the DualPlus, this reparenting may glitch the LDB so that it
permanently locks up.

By removing the reparenting in this commit, producing this glitch is
avoided. The device tree[1] can elect to reinstate the reparenting:

	&clks {
		assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
				  <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
		assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
					 <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>;
	};

Follow-up patches will explicitly check for this and do reparenting
defined this way in a glitch-free manner.

As of v2019.07.0, following mainline boards are potentially broken
by this (i.e. they're supported by barebox, are in the list above,
had a LDB enabled and might be defining CONFIG_DRIVER_VIDEO_IMX_IPUV3):
  - imx6qdl-zii-rdu2.dtsi
  - imx6qdl-udoo.dtsi
  - imx6qdl-mba6x.dtsi
  - imx6q-var-custom.dts
  - imx6q-guf-santaro.dts
  - imx6q-embedsky-e9.dtsi

[1]: If barebox is configured to show a boot splash screen, this snippet
     should exist in the barebox device tree. If barebox acts on it, the
     kernel will show following warning:
         ccm: ldb_di0_sel already changed from reset value: 0
         ccm: ldb_di1_sel already changed from reset value: 0
     This warning is safe to ignore.

Cc: Andrey Smirnov <andrew.smirnov@gmail.com>
Cc: Raphael Poggi <poggi.raph@gmail.com>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Tested-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: imx6: Mask mmdc_ch1 handshake for periph2_sel and mmdc_ch1_axi_podf ...

MMDC CH1 is not used on i.MX6Q, so the handshake needed to change the
parent of periph2_sel or the divider of mmdc_ch1_axi_podf will never
succeed.
Disable the handshake mechanism to allow changing the frequency of
mmdc_ch1_axi, allowing to use it as a possible source for the LDB DI
clock.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
[afa: reviewed for barebox]
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Tested-by: Andrey Smirnov <andrew.smirnov@gmail.com>
[afa: ported to barebox from Linux commit f13abeff2c]
[afa: moved call site to where it would've been moved in following commit]
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: imx6: fix use of cpu_is_mx6* before they are initialized ...

The cpu_is_mx6* macros rely on __imx_cpu_type, which is initialized
dependent on device tree compatible at "postcore" init-level imx_init.

The imx6q-ccm driver, which uses the cpu_is_mx6* macros, is registered
at "core" init-level, however. This results on the macro always returning
false.

Fix this by using the cpu_mx6_is_mx6* family of macros instead.
These already require that that CPU is a MX6, which is safe because the
the driver only matches against "fsl,imx6q-ccm".

Only exception is the video5 pll reparenting. Here we will just
maintain the old behavior as we will drop the if clause in a following
commit anyway.

Reported-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: divider: export clk_div_mask() helper ...

commit e6d3cc7 Linux upstream.

  clk: divider: export clk_div_mask() helper

  Export clk_div_mask() in clk-provider header so every clock providers
  derived from the generic clock divider may share the definition instead
  of redefining it.

  Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
  Signed-off-by: Michael Turquette <mturquette@baylibre.com>
  Signed-off-by: Stephen Boyd <sboyd@kernel.org>

Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: divider: Make generic for usage elsewhere ...

commit bca9690 Linux upstream adjusted
to current Barebox codebase.

  clk: divider: Make generic for usage elsewhere

  Some devices don't use mmio to interact with dividers. Split out the
  logic from the register read/write parts so that we can reuse the
  division logic elsewhere.

  Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
  Tested-by: Kenneth Westfield <kwestfie@codeaurora.org>
  Signed-off-by: Michael Turquette <mturquette@linaro.org>

Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: divider: Fix best div calculation for power-of-two and table dividers ...

commit dd23c2c Linux upstream.

  clk: divider: Fix best div calculation for power-of-two and table dividers

  The divider returned by clk_divider_bestdiv() is likely to be invalid in case
  of power-of-two and table dividers when CLK_SET_RATE_PARENT flag isn't set.

  Fixes boot on STiH416 platform.

  Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
  Signed-off-by: Mike Turquette <mturquette@linaro.org>
  [mturquette@linaro.org: trivial merge conflict & updated changelog]

Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: divider: Remove unused variable in clk_divider_recalc_rate ...

commit "clk: add divider_recalc_rate helper" reworked
clk_divider_recalc_rate() function and as part of that left one variable
assignment, which is not used later.

Fixes: e27c0b64db01 ("clk: add divider_recalc_rate helper")
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Merge branch 'for-next/imx'

clk: at91: fix warning about missing const-safety ...

compiling clk-main.c and clk-generated.c results in:

warning: passing argument 1 of 'memcpy' discards 'const' qualifier from
pointer target type [-Wdiscarded-qualifiers]
  memcpy(clkmain->clk.parent_names, parent_names, parents_array_size);
           ~~~~~~~~~~~~^~~~~~~~~~~~~

Avoid this by replacing the xzalloc+memcpy pair with xmemdup.
Zero-initialization of the buffer isn't necessary, because
memcpy spans the whole buffer.

Reviewed-by: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: imx: vf610: correct __iomem 'qualifier' placement ...

__iomem applies to the IOMEM() pointee, not to the auto pointer
that points at it. Move the annotation to correct this.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: at91: delete dead i2s/audio code ...

They aren't used anywhere, thus drop them.

Suggested-by: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Reviewed-by: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: at91: fix compilation errors in sama5d2.c ...

sama5d2.c was added alongside the update to the remaining clk drivers
to support the new upstream device tree bindings, but wasn't wired in
anywhere.

To prepare for usage in future sama5d2 support, fix compilation errors
related to absence of locks and unavailability of audio/i2s clock/pll
handling.

With this change, there are no users for the few definition-less at91
audio/i2s registration function declarations. So remove those as well.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Reviewed-by: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: vf610: improve handling case that cpu frequency can't be changed ...

Currently we get a nasty error message if the cpu clock can't be
changed:
DDRC is clocked by PLL1, can't switch CPU clockinitcall vf610_switch_cpu_clock+0x1/0x198 failed: Invalid argument

So let's do the following:
- factor out the check from vf610_switch_cpu_clock_to_500mhz() and
  vf610_switch_cpu_clock_to_400mhz
- if clock can't be changed, don't treat it as an error
- don't call clock notifier chain if clock can't be changed
- add trailing newline to the warning message

Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Reviewed-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: i.MX25: Add some more clocks ...

Add some clocks needed for:
- RNGB
- SCC
- Dryice RTC

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: socfpga: fix compiler warnings for Cyclone5 ...

When building for Cyclone5 SoCFPGA, the socfpga_a10_pll_init(),
socfpga_a10_perith_init() and socfpga_a10_gate_init() functions are
defined as dummy functions returning ERR_PTR(-ENOSYS).  They are defined
with external linkage.  With '-Wmissing-prototypes' GCC warns about
externally linked function definitions with no preceding prototype.
Define them as 'static inline' to avoid the compiler warnings.

(Note: Arria10 uses non-dummy versions of these functions declared
'extern' but defined elsewhere.)

Signed-off-by: Ian Abbott <abbotti@mev.co.uk>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Merge branch 'for-next/zynqmp'