Merge branch 'for-next/mxs'

Merge branch 'for-next/misc'

Merge branch 'for-next/kconfig'

Merge branch 'for-next/cpsw'

net: designware: eqos: attach PHY earlier ...

If the PHY isn't driving the refclock, the software reset of the
controller will time out. Some PHYs need some board specific
configuration to properly drive the reflock. Attach the PHY before
attempting the software reset, so PHY fixups have a chance to run.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

drivers: mark first batch of compilable drivers for COMPILE_TEST ...

All of these drivers have a runtime dependency on SoC peripherals, but
can nevertheless be compile-tested. Add COMPILE_TEST as an alternate
dependency.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

net: fec_imx: Return with an error when mandatory clock is missing ...

When a mandatory clock is missing we have to return with an error. Just
breaking out of the loop results in ignoring the error.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

net: fec_imx: Make ptp clock optional ...

The ptp clock doesn't exist on all SoCs, make it optional. In fact it
was optional before due to a bug in the driver.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

net: cpsw: make cpsw_send directional ...

For dual_emac mode, the driver needs to send on the individual
ports. We set the directional bits on each packet so the controller
knows where to send its.

From TI am335x Reference Manual:

14.3.2.10.2 Dual Mac Mode

- Packets from the host (port 0) to ports 1 and 2 should be directed.

Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

net: cpsw: add vlan handling for dual_emac mode ...

From TI am335x Reference Manual:

14.3.2.10.2 Dual Mac Mode

When operating in dual mac mode the intention is to transfer packets
between ports 0 and 1 and ports 0 and 2, but not between ports 1 and 2.

Each CPGMAC_SL appears as a single MAC with no bridging between MAC’s.
Each CPGMAC_SL has at least one unique (not the same) mac address.

Dual mac mode is configured as described below:

- Set the ale_vlan_aware bit in the ALE_Control register. This bit
configures the ALE to process in vlan aware mode.

With X can be Port 1 or Port 2:

- Configure the Port X to Port 0 VLAN.
Add a VLAN Table Entry with ports 0 and X as members (clear the flood
masks).

Add a VLAN/Unicast Address Table Entry with the PortX/0 VLAN and
a port number of 0.

- Select the dual mac mode on the port 0 FIFO by setting
tx_in_sel[1:0] = 01 in P0_Tx_In_Ctl.

Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

net: cpsw: cpsw_process should only handle rx channels for its own port ...

The driver is currently processing the whole channel list, so it is
possible that it handles a channel of the wrong interface. We limit the
rx_chan handling for its desired port.

The cpsw_send is removing finished tx_chan transfers on each send, so this
has no directional limitation.

Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

net: cpsw: move generic setup code to probe ...

All generic cpsw code can move to probe, so the controller is only reset
and configured once.

Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

net: cpsw: fix cpsw_slave_regs register offsets ...

The cpsw_slave_regs struct also start with max_blks register, so here we
also have to skip the first two bytes like for .host_port_reg_ofs

Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

net: enc28j60: fix typo in referenced Kconfig option ...

There is no ENC28J60_WRITEVERIFY, instead the Kconfig file defines
DRIVER_NET_ENC28J60_WRITEVERIFY. This has been this way since the very
first commit adding the driver.

The option is off by default, so this shouldn't break anything that
didn't mess with the option. Fix the typo.

Signed-off-by: Ahmad Fatoum <ahmad@a3f.at>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

net: remove unused Kconfig options ...

Both options are used nowhere and can be dropped:

- OF_NET code is compiled always and code is discarded at link-time if
  unreferenced
- Designware Ethernet can be enabled in Kconfig and no arch code
  selects the symbol

Signed-off-by: Ahmad Fatoum <ahmad@a3f.at>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Merge branch 'for-next/usb'

net: phy: Also print link down messages ...

Not only print when the link comes up, but also when it goes down.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

net: phy: Do not claim the link is up initially ...

A freshly created phy device doesn't have the link up, so drop setting
phydev->link to one initially.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

net: phy: mdio-mux: Use mdiobus_read/write() ...

We have mdiobus_read/write(), so use it rather than accessing the driver
hooks directly.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

net: fec_imx: Do not clear MII interrupt during receive ...

fec_recv() can be triggered during a MDIO access. so we may not clear
the FEC_IEVENT_MII interrupt the MDIO access is waiting for. Clearing
it in that moment causes the MDIO access to timeout.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

usb: net: Add support for the Asix AX88179 ...

This adds support for the Asix AX88179 USB3.0 ethernet converter chip.
The driver is based on the kernel driver with influence from the U-Boot
driver.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

net: usb: add hook for link changes ...

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

usb: net: Allocate tx buffer dynamically ...

It's cleaner to have a tx buffer per device and not one for all.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

usb: net: Allocate rx buffer dynamically ...

Allocate an individual rx buffer per device in the size we need it
instead of using one global buffer for all devices.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

net: designware: eqos: mimic Linux gmac4 mdio_{read, write} ...

The code was ported over from U-Boot and has some things different than
the Kernel driver:

- It reads ->mdio_address, but the kernel driver doesn't
- It doesn't write ->mdio_data in a read, but the kernel driver does
- It has delays in addition to spinning on MII_BUSY, but the kernel driver
  doesn't

Adopt the same flow as used by the kernel.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

net: designware: eqos: remove left-over PHY quirk work around ...

The dummy read was a left over from an abandoned merge with the existing
support for the SoCFPGA variant of the Designware MAC. It doesn't exist
in either the U-Boot or kernel drivers for the EQOS, thus drop it.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

net: designware: eqos: stm32: drop no longer needed syscfg-clk ...

The upstream device tree no longer lists "syscfg-clk" and the syscon node
contains a clocks property that the barebox syscon driver now
automatically clocks before access.

Thus drop the requirement that "syscfg-clk" is specified.

Fixes: 4aaceef58 ("dts: update to v5.6-rc1")
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

net: designware: socfpga: fix possible invalid pointer deref ...

In cases where the reset controller specification in the device tree is
malformed, we get an error pointer back from reset_control_get. This
compares unequal to NULL and would cause an access violation when passed
to reset_control_(de)?assert.

Fix this by propagating the error. When the reset controller is missing,
reset_control_(de)?assert will be passed NULL pointers, rendering them
no-ops.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

net: designware: eqos: don't funnel all MDIO writes to register 0 ...

eqos_mdio_write ended up using the addr parameter instead of the
computed miiaddr variable, which would've factored in the reg parameter.

This had the effect that all writes went to PHY register 0, which was
fine as long as there were only register 0 writes. As soon there are more
writes, e.g. because a PHY driver was enabled, register 0 became
clobbered and erratic behavior ensued.
Fix the typo and while at it rename the val parameter to a more
descriptive name.

Fixes: a4f709bbb ("net: add Designware Ethernet QoS for STM32MP")
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

net: fsl-fman: Do not put hardware in reset before Linux start ...

Linux depends on the icid values configured in the DPAA. Do not put
the hardware into reset in order to preserve the register values.
Without this, the IOMMU doesn't work properly.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>