From 3a29660ebc69c11fc841a662e8692e59c45eda10 Mon Sep 17 00:00:00 2001
From: Yann Gautier <yann.gautier@st.com>
Date: Tue, 21 May 2019 18:32:14 +0200
Subject: [PATCH 2/7] arch: rename CNTBaseN register offsets defines

The CNTFRQ already has a CNTBASEN_ prefix.
To be able to use CNTP_CTL from CP15, the CNTP_CTL define is renamed
CNTBASEN_CNTP_CTL.
To keep consistency, CNTPCT_LO and CNTP_CVAL_LO are also prefixed.

Change-Id: Ie328daa694a708130ee369218b57c0f4b08f7f44
Signed-off-by: Yann Gautier <yann.gautier@st.com>
---
 include/arch/aarch32/arch.h | 6 +++---
 include/arch/aarch64/arch.h | 6 +++---
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/include/arch/aarch32/arch.h b/include/arch/aarch32/arch.h
index 20175481f..047770e4f 100644
--- a/include/arch/aarch32/arch.h
+++ b/include/arch/aarch32/arch.h
@@ -457,13 +457,13 @@
  * system level implementation of the Generic Timer.
  ******************************************************************************/
 /* Physical Count register. */
-#define CNTPCT_LO		U(0x0)
+#define CNTBASEN_CNTPCT_LO		U(0x0)
 /* Counter Frequency register. */
 #define CNTBASEN_CNTFRQ		U(0x10)
 /* Physical Timer CompareValue register. */
-#define CNTP_CVAL_LO		U(0x20)
+#define CNTBASEN_CNTP_CVAL_LO	U(0x20)
 /* Physical Timer Control register. */
-#define CNTP_CTL		U(0x2c)
+#define CNTBASEN_CNTP_CTL	U(0x2c)
 
 /* Physical timer control register bit fields shifts and masks */
 #define CNTP_CTL_ENABLE_SHIFT   0
diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h
index 3ff2912f1..307dad585 100644
--- a/include/arch/aarch64/arch.h
+++ b/include/arch/aarch64/arch.h
@@ -670,13 +670,13 @@
  * system level implementation of the Generic Timer.
  ******************************************************************************/
 /* Physical Count register. */
-#define CNTPCT_LO		U(0x0)
+#define CNTBASEN_CNTPCT_LO		U(0x0)
 /* Counter Frequency register. */
 #define CNTBASEN_CNTFRQ		U(0x10)
 /* Physical Timer CompareValue register. */
-#define CNTP_CVAL_LO		U(0x20)
+#define CNTBASEN_CNTP_CVAL_LO	U(0x20)
 /* Physical Timer Control register. */
-#define CNTP_CTL		U(0x2c)
+#define CNTBASEN_CNTP_CTL	U(0x2c)
 
 /* PMCR_EL0 definitions */
 #define PMCR_EL0_RESET_VAL	U(0x0)
-- 
2.27.0