#! armcc -E

; 512 KB APROM
#if !defined(MBED_APP_START)
  #define MBED_APP_START            0x00000000
#endif

#if !defined(MBED_APP_SIZE)
  #define MBED_APP_SIZE             0x00080000
#endif

; 64 KB SRAM (internal)
#if !defined(MBED_RAM_START)
  #define MBED_RAM_START            0x20000000
#endif

#if !defined(MBED_RAM_SIZE)
  #define MBED_RAM_SIZE             0x00010000
#endif


; 1 MB SRAM (external)
#define MBED_RAM1_START             0x60000000
#define MBED_RAM1_SIZE              0x00100000

#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE)
  #define MBED_CONF_TARGET_BOOT_STACK_SIZE      0x400
#endif

#define VECTOR_SIZE                 (4*(16 + 142))

LR_IROM1  MBED_APP_START  MBED_APP_SIZE  {
  ER_IROM1  MBED_APP_START  MBED_APP_SIZE  {  ; load address = execution address
   *(RESET, +First)
   *(InRoot$$Sections)
   .ANY (+RO)
  }

  ARM_LIB_STACK  MBED_RAM_START  EMPTY  MBED_CONF_TARGET_BOOT_STACK_SIZE {
  }

  /* VTOR[TBLOFF] alignment requires:
   *
   * 1. Minumum 32-word
   * 2. Rounding up to the next power of two of table size
   */
  ER_IRAMVEC  AlignExpr(+0, 1024)  EMPTY  VECTOR_SIZE  {  ; Reserve for vectors
  }

  RW_m_crash_data  AlignExpr(+0, 0x100)  EMPTY  0x100  { ; Reserve for crash data storage
  }

  RW_IRAM1  AlignExpr(+0, 16)  {  ; 16 byte-aligned
   .ANY (+RW +ZI)
  }

  ; Too large to place into internal SRAM. So place into external SRAM instead.
  ER_XRAM1  MBED_RAM1_START  {
    *sal-stack-lwip* (+ZI)
  }
  
  ; Extern SRAM for HEAP
  ARM_LIB_HEAP  AlignExpr(+0, 16)  EMPTY  (MBED_RAM1_START + MBED_RAM1_SIZE - AlignExpr(ImageLimit(ER_XRAM1), 16))  {
  }
}
ScatterAssert(LoadLimit(LR_IROM1) <= (MBED_APP_START + MBED_APP_SIZE))    ; 512 KB APROM
ScatterAssert(ImageLimit(RW_IRAM1) <= (MBED_RAM_START + MBED_RAM_SIZE))   ; 64 KB SRAM (internal)
ScatterAssert(ImageLimit(ARM_LIB_HEAP) <= (MBED_RAM1_START + MBED_RAM1_SIZE))   ; 1 MB SRAM (external)