{ "name": "stm32-emac", "config": { "eth-rxbufnb": 4, "eth-txbufnb": 4, "thread-stacksize": { "help": "Stack size for stm32_emac_thread", "value": 1024 }, "eth-phy-address": { "help" : "Configures actual PHY address according to pullup/down status of PHYAD pin(s)", "value" : 0 }, "eth-phy-media-interface": { "help" : "Selects Connection to PHY Chip: ETH_MEDIA_INTERFACE_RMII / ETH_MEDIA_INTERFACE_MII", "value" : "ETH_MEDIA_INTERFACE_RMII" }, "eth-phy-AutoNegotiation": { "help" : "Selects AutoNegotiation mode : ETH_AUTONEGOTIATION_ENABLE / ETH_AUTONEGOTIATION_DISABLE", "value" : "ETH_AUTONEGOTIATION_ENABLE" }, "eth-phy-DuplexMode": { "help" : "Selects DuplexMode mode : ETH_MODE_FULLDUPLEX / ETH_MODE_HALFDUPLEX", "value" : "ETH_MODE_FULLDUPLEX" }, "eth-phy-Speed": { "help" : "Selects Speed mode : ETH_SPEED_100M / ETH_SPEED_10M", "value" : "ETH_SPEED_100M" }, "eth-phy-reset-delay": { "help" : "Reset process time - Default value: 0.5s as specified in LAN8742A datasheet", "value" : "500" }, "eth-phy-status-register": { "help" : "PHY register Offset with auto-negotiation result - Default value is LAN8742A PHY Special Control/Status Register", "value" : "31" }, "eth-phy-speed-status": { "help" : "Speed mask information in eth-phy-status-register", "value" : "0x0004" }, "eth-phy-duplex-status": { "help" : "Duplex mask information in eth-phy-status-register", "value" : "0x0010" } }, "target_overrides": { "NUCLEO_F207ZG": { "eth-rxbufnb": 2, "eth-txbufnb": 4 }, "STM32H7": { "eth-txbufnb": 10 }, "ARCH_MAX": { "eth-phy-address": 1 } } }