#! armcc -E
/*
** ###################################################################
**     Processors:          LPC54114J256BD64_cm4
**                          LPC54114J256UK49_cm4
**
**     Compiler:            Keil ARM C/C++ Compiler
**     Reference manual:    LPC5411x User manual Rev. 1.0 16 February 2016
**     Version:             rev. 1.0, 2016-04-29
**     Build:               b160526
**
**     Abstract:
**         Linker file for the Keil ARM C/C++ Compiler
**
**     Copyright (c) 2016 Freescale Semiconductor, Inc.
**     Copyright (c) 2016 NXP
**     All rights reserved.
**
**     Redistribution and use in source and binary forms, with or without modification,
**     are permitted provided that the following conditions are met:
**
**     o Redistributions of source code must retain the above copyright notice, this list
**       of conditions and the following disclaimer.
**
**     o Redistributions in binary form must reproduce the above copyright notice, this
**       list of conditions and the following disclaimer in the documentation and/or
**       other materials provided with the distribution.
**
**     o Neither the name of copyright holder nor the names of its
**       contributors may be used to endorse or promote products derived from this
**       software without specific prior written permission.
**
**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**
**     http:                 www.nxp.com
**     mail:                 support@nxp.com
**
** ###################################################################
*/
#define __ram_vector_table__            1

#if (defined(__ram_vector_table__))
  #define __ram_vector_table_size__    0x000000E0
#else
  #define __ram_vector_table_size__    0x00000000
#endif

#define m_interrupts_start             0x00000000
#define m_interrupts_size              0x000000E0

#define m_text_start                   0x000000E0
#define m_text_size                    0x0002FF20

#define m_core1_image_start            0x00030000
#define m_core1_image_size             0x00010000

#define m_interrupts_ram_start         0x20000000
#define m_interrupts_ram_size          __ram_vector_table_size__

#define m_rpmsg_sh_mem_start           0x20026800
#define m_rpmsg_sh_mem_size            0x00001800

#define m_data_start                   (m_interrupts_ram_start + m_interrupts_ram_size)
#define m_data_size                    (0x00010000 - m_interrupts_ram_size)

#define m_sramx_start                  0x04000000
#define m_sramx_size                   0x00008000

/* Sizes */
#if (defined(__stack_size__))
  #define Stack_Size                   __stack_size__
#else
  #define Stack_Size                   0x0400
#endif

#if (defined(__heap_size__))
  #define Heap_Size                    __heap_size__
#else
  #define Heap_Size                    0x0400
#endif

LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load region size_region
  VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address
    * (RESET,+FIRST)
  }
  ER_m_text m_text_start m_text_size  {  ; load address = execution address
    * (InRoot$$Sections)
    .ANY (+RO)
  }
  ER_m_sramx m_sramx_start m_sramx_size { ; SRAMX memory
    * (sramx)
  }

#if (defined(__ram_vector_table__))
  VECTOR_RAM m_interrupts_ram_start EMPTY m_interrupts_ram_size {
  }
#else
  VECTOR_RAM m_interrupts_start EMPTY 0 {
  }
#endif

  RW_m_data m_data_start m_data_size  {  ; RW data
    .ANY (+RW +ZI)
  }
  RW_IRAM1 ((ImageLimit(RW_m_data) == m_data_start) ? ImageLimit(RW_m_data) : +0) EMPTY Heap_Size { ; Heap region growing up
  }
  ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
  }

  RPMSG_SH_MEM m_rpmsg_sh_mem_start UNINIT m_rpmsg_sh_mem_size { ; Shared memory used by RPMSG
    * (rpmsg_sh_mem_section)
  }
}

LR_CORE1_IMAGE m_core1_image_start {
  CORE1_REGION m_core1_image_start m_core1_image_size {
    *(M0CODE)
  }
}