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/******************************************************************************* * DISCLAIMER * This software is supplied by Renesas Electronics Corporation and is only * intended for use with Renesas products. No other uses are authorized. This * software is owned by Renesas Electronics Corporation and is protected under * all applicable laws, including copyright laws. * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. * Renesas reserves the right, without notice, to make changes to this software * and to discontinue the availability of this software. By using this software, * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer * Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /* Copyright (c) 2018-2020 Renesas Electronics Corporation. * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ /******************************************************************************* * Rev: 2.00 * Description : IO bitmask header *******************************************************************************/ #ifndef BSC_IOBITMASK_H #define BSC_IOBITMASK_H /* ==== Mask values for IO registers ==== */ #define BSC_CMNCR_HIZCNT (0x00000001u) #define BSC_CMNCR_HIZCNT_SHIFT (0u) #define BSC_CMNCR_HIZMEM (0x00000002u) #define BSC_CMNCR_HIZMEM_SHIFT (1u) #define BSC_CMNCR_DPRTY (0x00000600u) #define BSC_CMNCR_DPRTY_SHIFT (9u) #define BSC_CMNCR_AL0 (0x01000000u) #define BSC_CMNCR_AL0_SHIFT (24u) #define BSC_CMNCR_TL0 (0x10000000u) #define BSC_CMNCR_TL0_SHIFT (28u) #define BSC_CS0BCR_BSZ (0x00000600u) #define BSC_CS0BCR_BSZ_SHIFT (9u) #define BSC_CS0BCR_TYPE (0x00007000u) #define BSC_CS0BCR_TYPE_SHIFT (12u) #define BSC_CS0BCR_IWRRS (0x00070000u) #define BSC_CS0BCR_IWRRS_SHIFT (16u) #define BSC_CS0BCR_IWRRD (0x00380000u) #define BSC_CS0BCR_IWRRD_SHIFT (19u) #define BSC_CS0BCR_IWRWS (0x01C00000u) #define BSC_CS0BCR_IWRWS_SHIFT (22u) #define BSC_CS0BCR_IWRWD (0x0E000000u) #define BSC_CS0BCR_IWRWD_SHIFT (25u) #define BSC_CS0BCR_IWW (0x70000000u) #define BSC_CS0BCR_IWW_SHIFT (28u) #define BSC_CS1BCR_BSZ (0x00000600u) #define BSC_CS1BCR_BSZ_SHIFT (9u) #define BSC_CS1BCR_TYPE (0x00007000u) #define BSC_CS1BCR_TYPE_SHIFT (12u) #define BSC_CS1BCR_IWRRS (0x00070000u) #define BSC_CS1BCR_IWRRS_SHIFT (16u) #define BSC_CS1BCR_IWRRD (0x00380000u) #define BSC_CS1BCR_IWRRD_SHIFT (19u) #define BSC_CS1BCR_IWRWS (0x01C00000u) #define BSC_CS1BCR_IWRWS_SHIFT (22u) #define BSC_CS1BCR_IWRWD (0x0E000000u) #define BSC_CS1BCR_IWRWD_SHIFT (25u) #define BSC_CS1BCR_IWW (0x70000000u) #define BSC_CS1BCR_IWW_SHIFT (28u) #define BSC_CS2BCR_BSZ (0x00000600u) #define BSC_CS2BCR_BSZ_SHIFT (9u) #define BSC_CS2BCR_TYPE (0x00007000u) #define BSC_CS2BCR_TYPE_SHIFT (12u) #define BSC_CS2BCR_IWRRS (0x00070000u) #define BSC_CS2BCR_IWRRS_SHIFT (16u) #define BSC_CS2BCR_IWRRD (0x00380000u) #define BSC_CS2BCR_IWRRD_SHIFT (19u) #define BSC_CS2BCR_IWRWS (0x01C00000u) #define BSC_CS2BCR_IWRWS_SHIFT (22u) #define BSC_CS2BCR_IWRWD (0x0E000000u) #define BSC_CS2BCR_IWRWD_SHIFT (25u) #define BSC_CS2BCR_IWW (0x70000000u) #define BSC_CS2BCR_IWW_SHIFT (28u) #define BSC_CS3BCR_BSZ (0x00000600u) #define BSC_CS3BCR_BSZ_SHIFT (9u) #define BSC_CS3BCR_TYPE (0x00007000u) #define BSC_CS3BCR_TYPE_SHIFT (12u) #define BSC_CS3BCR_IWRRS (0x00070000u) #define BSC_CS3BCR_IWRRS_SHIFT (16u) #define BSC_CS3BCR_IWRRD (0x00380000u) #define BSC_CS3BCR_IWRRD_SHIFT (19u) #define BSC_CS3BCR_IWRWS (0x01C00000u) #define BSC_CS3BCR_IWRWS_SHIFT (22u) #define BSC_CS3BCR_IWRWD (0x0E000000u) #define BSC_CS3BCR_IWRWD_SHIFT (25u) #define BSC_CS3BCR_IWW (0x70000000u) #define BSC_CS3BCR_IWW_SHIFT (28u) #define BSC_CS4BCR_BSZ (0x00000600u) #define BSC_CS4BCR_BSZ_SHIFT (9u) #define BSC_CS4BCR_TYPE (0x00007000u) #define BSC_CS4BCR_TYPE_SHIFT (12u) #define BSC_CS4BCR_IWRRS (0x00070000u) #define BSC_CS4BCR_IWRRS_SHIFT (16u) #define BSC_CS4BCR_IWRRD (0x00380000u) #define BSC_CS4BCR_IWRRD_SHIFT (19u) #define BSC_CS4BCR_IWRWS (0x01C00000u) #define BSC_CS4BCR_IWRWS_SHIFT (22u) #define BSC_CS4BCR_IWRWD (0x0E000000u) #define BSC_CS4BCR_IWRWD_SHIFT (25u) #define BSC_CS4BCR_IWW (0x70000000u) #define BSC_CS4BCR_IWW_SHIFT (28u) #define BSC_CS5BCR_BSZ (0x00000600u) #define BSC_CS5BCR_BSZ_SHIFT (9u) #define BSC_CS5BCR_TYPE (0x00007000u) #define BSC_CS5BCR_TYPE_SHIFT (12u) #define BSC_CS5BCR_IWRRS (0x00070000u) #define BSC_CS5BCR_IWRRS_SHIFT (16u) #define BSC_CS5BCR_IWRRD (0x00380000u) #define BSC_CS5BCR_IWRRD_SHIFT (19u) #define BSC_CS5BCR_IWRWS (0x01C00000u) #define BSC_CS5BCR_IWRWS_SHIFT (22u) #define BSC_CS5BCR_IWRWD (0x0E000000u) #define BSC_CS5BCR_IWRWD_SHIFT (25u) #define BSC_CS5BCR_IWW (0x70000000u) #define BSC_CS5BCR_IWW_SHIFT (28u) #define BSC_CS0WCR_0_HW (0x00000003u) #define BSC_CS0WCR_0_HW_SHIFT (0u) #define BSC_CS0WCR_0_WM (0x00000040u) #define BSC_CS0WCR_0_WM_SHIFT (6u) #define BSC_CS0WCR_0_WR (0x00000780u) #define BSC_CS0WCR_0_WR_SHIFT (7u) #define BSC_CS0WCR_0_SW (0x00001800u) #define BSC_CS0WCR_0_SW_SHIFT (11u) #define BSC_CS0WCR_0_BAS (0x00100000u) #define BSC_CS0WCR_0_BAS_SHIFT (20u) #define BSC_CS0WCR_1_WM (0x00000040u) #define BSC_CS0WCR_1_WM_SHIFT (6u) #define BSC_CS0WCR_1_W (0x00000780u) #define BSC_CS0WCR_1_W_SHIFT (7u) #define BSC_CS0WCR_1_BW (0x00030000u) #define BSC_CS0WCR_1_BW_SHIFT (16u) #define BSC_CS0WCR_1_BST (0x00300000u) #define BSC_CS0WCR_1_BST_SHIFT (20u) #define BSC_CS0WCR_2_WM (0x00000040u) #define BSC_CS0WCR_2_WM_SHIFT (6u) #define BSC_CS0WCR_2_W (0x00000780u) #define BSC_CS0WCR_2_W_SHIFT (7u) #define BSC_CS0WCR_2_BW (0x00030000u) #define BSC_CS0WCR_2_BW_SHIFT (16u) #define BSC_CS1WCR_0_HW (0x00000003u) #define BSC_CS1WCR_0_HW_SHIFT (0u) #define BSC_CS1WCR_0_WM (0x00000040u) #define BSC_CS1WCR_0_WM_SHIFT (6u) #define BSC_CS1WCR_0_WR (0x00000780u) #define BSC_CS1WCR_0_WR_SHIFT (7u) #define BSC_CS1WCR_0_SW (0x00001800u) #define BSC_CS1WCR_0_SW_SHIFT (11u) #define BSC_CS1WCR_0_WW (0x00070000u) #define BSC_CS1WCR_0_WW_SHIFT (16u) #define BSC_CS1WCR_0_BAS (0x00100000u) #define BSC_CS1WCR_0_BAS_SHIFT (20u) #define BSC_CS2WCR_0_WM (0x00000040u) #define BSC_CS2WCR_0_WM_SHIFT (6u) #define BSC_CS2WCR_0_WR (0x00000780u) #define BSC_CS2WCR_0_WR_SHIFT (7u) #define BSC_CS2WCR_0_BAS (0x00100000u) #define BSC_CS2WCR_0_BAS_SHIFT (20u) #define BSC_CS2WCR_1_A2CL (0x00000180u) #define BSC_CS2WCR_1_A2CL_SHIFT (7u) #define BSC_CS3WCR_1_WTRC (0x00000003u) #define BSC_CS3WCR_1_WTRC_SHIFT (0u) #define BSC_CS3WCR_1_TRWL (0x00000018u) #define BSC_CS3WCR_1_TRWL_SHIFT (3u) #define BSC_CS3WCR_1_A3CL (0x00000180u) #define BSC_CS3WCR_1_A3CL_SHIFT (7u) #define BSC_CS3WCR_1_WTRCD (0x00000C00u) #define BSC_CS3WCR_1_WTRCD_SHIFT (10u) #define BSC_CS3WCR_1_WTRP (0x00006000u) #define BSC_CS3WCR_1_WTRP_SHIFT (13u) #define BSC_CS3WCR_0_WM (0x00000040u) #define BSC_CS3WCR_0_WM_SHIFT (6u) #define BSC_CS3WCR_0_WR (0x00000780u) #define BSC_CS3WCR_0_WR_SHIFT (7u) #define BSC_CS3WCR_0_BAS (0x00100000u) #define BSC_CS3WCR_0_BAS_SHIFT (20u) #define BSC_CS4WCR_0_HW (0x00000003u) #define BSC_CS4WCR_0_HW_SHIFT (0u) #define BSC_CS4WCR_0_WM (0x00000040u) #define BSC_CS4WCR_0_WM_SHIFT (6u) #define BSC_CS4WCR_0_WR (0x00000780u) #define BSC_CS4WCR_0_WR_SHIFT (7u) #define BSC_CS4WCR_0_SW (0x00001800u) #define BSC_CS4WCR_0_SW_SHIFT (11u) #define BSC_CS4WCR_0_WW (0x00070000u) #define BSC_CS4WCR_0_WW_SHIFT (16u) #define BSC_CS4WCR_0_BAS (0x00100000u) #define BSC_CS4WCR_0_BAS_SHIFT (20u) #define BSC_CS4WCR_1_HW (0x00000003u) #define BSC_CS4WCR_1_HW_SHIFT (0u) #define BSC_CS4WCR_1_WM (0x00000040u) #define BSC_CS4WCR_1_WM_SHIFT (6u) #define BSC_CS4WCR_1_W (0x00000780u) #define BSC_CS4WCR_1_W_SHIFT (7u) #define BSC_CS4WCR_1_SW (0x00001800u) #define BSC_CS4WCR_1_SW_SHIFT (11u) #define BSC_CS4WCR_1_BW (0x00030000u) #define BSC_CS4WCR_1_BW_SHIFT (16u) #define BSC_CS4WCR_1_BST (0x00300000u) #define BSC_CS4WCR_1_BST_SHIFT (20u) #define BSC_CS5WCR_0_HW (0x00000003u) #define BSC_CS5WCR_0_HW_SHIFT (0u) #define BSC_CS5WCR_0_WM (0x00000040u) #define BSC_CS5WCR_0_WM_SHIFT (6u) #define BSC_CS5WCR_0_WR (0x00000780u) #define BSC_CS5WCR_0_WR_SHIFT (7u) #define BSC_CS5WCR_0_SW (0x00001800u) #define BSC_CS5WCR_0_SW_SHIFT (11u) #define BSC_CS5WCR_0_WW (0x00070000u) #define BSC_CS5WCR_0_WW_SHIFT (16u) #define BSC_CS5WCR_0_MPXWBAS (0x00100000u) #define BSC_CS5WCR_0_MPXWBAS_SHIFT (20u) #define BSC_CS5WCR_0_SZSEL (0x00200000u) #define BSC_CS5WCR_0_SZSEL_SHIFT (21u) #define BSC_SDCR_A3COL (0x00000003u) #define BSC_SDCR_A3COL_SHIFT (0u) #define BSC_SDCR_A3ROW (0x00000018u) #define BSC_SDCR_A3ROW_SHIFT (3u) #define BSC_SDCR_BACTV (0x00000100u) #define BSC_SDCR_BACTV_SHIFT (8u) #define BSC_SDCR_PDOWN (0x00000200u) #define BSC_SDCR_PDOWN_SHIFT (9u) #define BSC_SDCR_RMODE (0x00000400u) #define BSC_SDCR_RMODE_SHIFT (10u) #define BSC_SDCR_RFSH (0x00000800u) #define BSC_SDCR_RFSH_SHIFT (11u) #define BSC_SDCR_DEEP (0x00002000u) #define BSC_SDCR_DEEP_SHIFT (13u) #define BSC_SDCR_A2COL (0x00030000u) #define BSC_SDCR_A2COL_SHIFT (16u) #define BSC_SDCR_A2ROW (0x00180000u) #define BSC_SDCR_A2ROW_SHIFT (19u) #define BSC_RTCSR_RRC (0x00000007u) #define BSC_RTCSR_RRC_SHIFT (0u) #define BSC_RTCSR_CKS (0x00000038u) #define BSC_RTCSR_CKS_SHIFT (3u) #define BSC_RTCSR_CMIE (0x00000040u) #define BSC_RTCSR_CMIE_SHIFT (6u) #define BSC_RTCSR_CMF (0x00000080u) #define BSC_RTCSR_CMF_SHIFT (7u) #define BSC_TOSTR_CS0TOSTF (0x00000001u) #define BSC_TOSTR_CS0TOSTF_SHIFT (0u) #define BSC_TOSTR_CS1TOSTF (0x00000002u) #define BSC_TOSTR_CS1TOSTF_SHIFT (1u) #define BSC_TOSTR_CS2TOSTF (0x00000004u) #define BSC_TOSTR_CS2TOSTF_SHIFT (2u) #define BSC_TOSTR_CS3TOSTF (0x00000008u) #define BSC_TOSTR_CS3TOSTF_SHIFT (3u) #define BSC_TOSTR_CS4TOSTF (0x00000010u) #define BSC_TOSTR_CS4TOSTF_SHIFT (4u) #define BSC_TOSTR_CS5TOSTF (0x00000020u) #define BSC_TOSTR_CS5TOSTF_SHIFT (5u) #define BSC_TOENR_CS0TOEN (0x00000001u) #define BSC_TOENR_CS0TOEN_SHIFT (0u) #define BSC_TOENR_CS1TOEN (0x00000002u) #define BSC_TOENR_CS1TOEN_SHIFT (1u) #define BSC_TOENR_CS2TOEN (0x00000004u) #define BSC_TOENR_CS2TOEN_SHIFT (2u) #define BSC_TOENR_CS3TOEN (0x00000008u) #define BSC_TOENR_CS3TOEN_SHIFT (3u) #define BSC_TOENR_CS4TOEN (0x00000010u) #define BSC_TOENR_CS4TOEN_SHIFT (4u) #define BSC_TOENR_CS5TOEN (0x00000020u) #define BSC_TOENR_CS5TOEN_SHIFT (5u) #define BSC_ACADJ_SDRIDLY (0x0000000Fu) #define BSC_ACADJ_SDRIDLY_SHIFT (0u) #define BSC_ACADJ_SDRODLY (0x000F0000u) #define BSC_ACADJ_SDRODLY_SHIFT (16u) #endif