<?xml version="1.0" encoding="utf-8"?>


<!--****************************************************************************
* \file ctdac.cypersonality
* \version 1.0
*
* \brief
* CTDAC personality description file.
*
********************************************************************************
* \copyright
* Copyright 2018-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
*     http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*****************************************************************************-->

<Personality id="mxs40pass_ctdac" name="CTDAC" version="1.0" path="Analog/DAC" xmlns="http://cypress.com/xsd/cyhwpersonality_v1">
  <Dependencies>
    <IpBlock name="mxs40pass,mxs40pass_ver2" />
    <Resource name="pass\.ctdac" used="true" />
  </Dependencies>
  <ExposedMembers />
  <Parameters>
    <!-- PDL documentation -->
    <ParamDoc id="pdlDoc" name="Configuration Help" group="Peripheral Documentation" default="file:///`${cy_libs_path()}`/docs/pdl_api_reference_manual/html/group__group__ctdac.html" linkText="Open CTDAC Documentation" visible="true" desc="Opens the Peripheral Driver Library Documentation" />
  
    <!-- Internal variables to control visibility of other stuff -->
    <ParamString id="ctdac_instance" name="ctdac_instance" group="Internal" default="`${getInstNumber(&quot;ctdac&quot;)}`" visible="false" editable="false" desc="Internal variable for the CTDAC instance on the device" />
    <ParamBool id="hasCTB" name="hasCTB" group="Internal" default="`${hasBlock(&quot;pass[0].ctb[0].oa[0]&quot;)}`" visible="false" editable="false" desc="Check whether device has CTBs" />
    <!-- Internal variables to control visibility of other stuff -->

    <ParamChoice id="vref_source" name="Vref Source" group="General" default="vdda" visible="true" editable="true" desc="Configure the reference source for the CTDAC." >
      <Entry name="Vdda" value="vdda" visible="true" />
      <Entry name="External" value="external_pin" visible="`${hasCTB}`" /> <!-- how to handle which pin the user selects? restrict to a set of pins?-->
      <!-- MODUS-2327 filed to get Analog Reference as CTB.OA1 input
      <Entry name="Analog reference" value="external_aref" visible="`${hasCTB}`" />
      -->      
    </ParamChoice>

    <!--
    <ParamSignal name="External input" port="pass[0].ctb[`${ctdac_instance}`].oa[0].vplus[0]" group="General" visible="`${vref_source eq external_pin}`" desc="" canBeEmpty="false" />
    <ParamSignal name="External input 2" port="pass[0].ctb[0].oa[0].vplus[0]" group="General" visible="`${vref_source eq external_pin}`" desc="" canBeEmpty="true" />
-->

    <ParamChoice id="output_buffer" name="Output Buffer" group="General" default="unbuffered_pin" visible="true" editable="true" desc="Configure the output to be buffered or unbuffered." >
      <Entry name="Unbuffered to Pin" value="unbuffered_pin" visible="true" />
      <Entry name="Unbuffered Internal" value="unbuffered_internal" visible="true" />
      <Entry name="Buffered" value="buffered" visible="`${hasCTB}`" />      
    </ParamChoice>

    <!-- Internal variables to control visibility of other stuff -->
    <ParamString id="vref_source_is_vdda" name="vref_source_is_vdda" group="Internal" default="`${vref_source eq vdda}`" visible="false" editable="false" desc="Internal variable to check if Vref source is Vdda" />
    <ParamString id="ctb_used" name="ctb_used" group="Internal" default="`${(vref_source ne vdda) || (output_buffer eq buffered)}`" visible="false" editable="false" desc="Internal variable to check if any CTB opamp is used" />    
    <ParamString id="output_is_unbuffered" name="output_is_unbuffered" group="Internal" default="`${(output_buffer eq unbuffered_pin) || (output_buffer eq unbuffered_internal)}`" visible="false" editable="false" desc="Internal variable to check if output is unbuffered" />
    <!-- Internal variables to control visibility of other stuff -->

    <ParamChoice id="format_mode" name="Format" group="General" default="CY_CTDAC_FORMAT_UNSIGNED" visible="true" editable="true" desc="Configure the format in which the DAC value register is decoded." >
      <Entry name="12-bit Unsigned" value="CY_CTDAC_FORMAT_UNSIGNED" visible="true" />
      <Entry name="12-bit Two's-Complement (Signed)" value="CY_CTDAC_FORMAT_SIGNED" visible="true" />
    </ParamChoice>

    <ParamRange id="initial_code" name="Initial Code" group="General" default="0" min="`${(format_mode eq CY_CTDAC_FORMAT_UNSIGNED) ? 0 : -2048}`" max="`${(format_mode eq CY_CTDAC_FORMAT_UNSIGNED) ? 4095 : 2047}`" resolution="1" visible="true" editable="true" desc="The initial code in the DAC value and buffered value registers." />

    <ParamChoice id="update_mode" name="Update Mode" group="General" default="CY_CTDAC_UPDATE_BUFFERED_WRITE" visible="true" editable="true" desc="Configure how the DAC value is updated." >
      <Entry name="Direct Write" value="CY_CTDAC_UPDATE_DIRECT_WRITE" visible="true" />
      <Entry name="Buffered Write" value="CY_CTDAC_UPDATE_BUFFERED_WRITE" visible="true" />
      <!--<Entry name="Strobe edge sync" value="CY_CTDAC_UPDATE_STROBE_EDGE_SYNC" visible="true" />
      <Entry name="Strobe edge immediate" value="CY_CTDAC_UPDATE_STROBE_EDGE_IMMEDIATE" visible="true" />
      <Entry name="Strobe level" value="CY_CTDAC_UPDATE_STROBE_LEVEL" visible="true" />-->
    </ParamChoice>

    <ParamBool id="deep_sleep" name="Enable Deep Sleep Operation" group="General" default="false" visible="true" editable="true" desc="Configure whether the DAC is enabled in Deep Sleep mode." />

    <ParamSignal name="Clock" port="clock[0]" group="Connections" visible="`${update_mode ne CY_CTDAC_UPDATE_DIRECT_WRITE}`" desc="Clock that operates this block." canBeEmpty="`${update_mode eq CY_CTDAC_UPDATE_DIRECT_WRITE}`">
        <Constraint type="REQUIRE" targetLocation="peri\[\d+\]\.div_.*" valid="`${update_mode ne CY_CTDAC_UPDATE_DIRECT_WRITE}`" >
        <Parameter id="intDivider" severity="ERROR" reason="Clock frequency is '`${getExposedMember(&quot;REF_LOCATION&quot;, &quot;frequency&quot;) / 1000}` kHz', but must be less than 500 kHz for proper CTDAC operation.">
          <Range min="`${ceil(getExposedMember(&quot;REF_LOCATION&quot;, &quot;frequency&quot;) * getExposedMember(&quot;REF_LOCATION&quot;, &quot;divider&quot;) / 500000)}`" max="`${floor(getExposedMember(&quot;REF_LOCATION&quot;, &quot;frequency&quot;) * getExposedMember(&quot;REF_LOCATION&quot;, &quot;divider&quot;) / 1)}`" />
        </Parameter>
        </Constraint>
    </ParamSignal>
    <ParamString id="source_clk" name="Source Clock Resource" group="Connections" default="`${getBlockFromSignal(&quot;clock[0]&quot;)}`" visible="false" editable="false" desc="Source Clock Resource" />
    <ParamString id="clk_freq_hz" name="clk_freq_hz" group="Connections" default="`${(update_mode ne CY_CTDAC_UPDATE_DIRECT_WRITE) ? getExposedMember(source_clk, &quot;frequency&quot;) : 0}`" visible="false" editable="false" desc="CTDAC clock frequency in hertz" />
    <ParamString id="clk_freq_display" name="Clock Frequency" group="Connections" default="`${floor(clk_freq_hz / pow(10, 3))}` kHz" visible="`${update_mode ne CY_CTDAC_UPDATE_DIRECT_WRITE}`" editable="false" desc="Displayed CTDAC clock frequency in kHz" />

    <ParamSignal name="DAC Output" port="ctdvout[0]" group="Connections" visible="`${output_buffer ne unbuffered_pin}`" desc="Buffered DAC analog output connection." canBeEmpty="true" >
        <Constraint type="REQUIRE" targetLocation="pass\[\d+\]\.ctb\[0\]\.oa\[0\]\.vplus\[0\]" valid="`${output_buffer eq buffered}`" >        
        </Constraint>
    </ParamSignal>
    
    <ParamSignal name="DAC Output Unbuffered" port="ctdvoutsw[0]" group="Connections" visible="`${output_buffer eq unbuffered_pin}`" desc="Unbuffered DAC analog output to pin." canBeEmpty="true" >        
    </ParamSignal>
    
    <ParamSignal name="Reference Source" port="ctdrefdrive[0]" group="Connections" visible="`${vref_source eq external_pin}`" desc="External reference selection." canBeEmpty="true" >
        <Constraint type="REQUIRE" targetLocation="pass\[\d+\]\.ctb\[0\]\.oa\[1\]\.(out_1x|vminus)\[0\]" valid="`${vref_source eq external_pin}`" >        
        </Constraint>
    </ParamSignal>
    
    <ParamSignal name="Trigger Output" port="tr_ctdac_empty[0]" group="Connections" visible="true" desc="DAC trigger output connection." canBeEmpty="true" >
      <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" >
        <Parameter id="DriveModes" severity="DEFAULT" reason="">
          <Fixed value="CY_GPIO_DM_STRONG_IN_OFF" />
        </Parameter>
      </Constraint>
      <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" >
        <Parameter id="DriveModes" severity="INFO" reason="The pin Drive Mode parameter does not match expected.">
          <Fixed value="CY_GPIO_DM_STRONG_IN_OFF" />
        </Parameter>
      </Constraint>
      <Constraint type="ACCEPT" targetLocation=".*" valid="true" />
    </ParamSignal>
    <!--<ParamSignal name="Strobe Input" port="dsi_ctdac_strobe[0]" group="Connections" visible="true" desc="DAC trigger output connection." canBeEmpty="`${update_mode &lt; CY_CTDAC_UPDATE_STROBE_EDGE_SYNC}`" />-->

    <!--Advanced-->
    <ParamChoice id="output_mode" name="Output Mode" group="Advanced" default="CY_CTDAC_OUTPUT_VALUE" visible="true" editable="true" desc="Configure the DAC output mode to high-z, enabled and driving, or resisitve pulled to Vssa or Vref" >
      <Entry name="Output the Code Value" value="CY_CTDAC_OUTPUT_VALUE" visible="true" />
      <Entry name="Output the Code Value Plus 1" value="CY_CTDAC_OUTPUT_VALUE_PLUS1" visible="true" />
      <Entry name="High-Z the Output" value="CY_CTDAC_OUTPUT_HIGHZ" visible="true" />
      <Entry name="Connect Output to Vssa" value="CY_CTDAC_OUTPUT_VSSA" visible="true" />
      <Entry name="Connect Output to Vref" value="CY_CTDAC_OUTPUT_VREF" visible="true" />
    </ParamChoice>
    <ParamBool id="inFlash" name="Store Config in Flash" group="Advanced" default="true" visible="true" editable="true" desc="Controls whether the configuration structure is stored in flash (const, true) or SRAM (not const, false)." />

    <!-- Peripheral clock divider connection -->
    <ParamString id="pclk" name="PCLK" group="Internal" default="`${getBlockFromSignal(&quot;clock[0]&quot;)}`" visible="false" editable="false" desc="Connected peripheral clock divider (PCLK)." />
    <ParamBool id="pclkOk" name="PCLK Valid" group="Internal" default="`${hasConnection(&quot;clock&quot;, 0) &amp;&amp; isBlockUsed(pclk)}`" visible="false" editable="false" desc="Checks whether there is a PCLK connected and enabled." />
    <ParamString id="pclkDst" name="PCLK Destination" group="Internal" default="PCLK_PASS_CLOCK_CTDAC" visible="false" editable="false" desc="Generates PCLK connection define." />

  </Parameters>

  <DRCs>
    <!-- MODUS-2327 - An AREF personality is required which should have the DRC below
    <DRC type="ERROR" text="The Vref must be enabled for Deep Sleep operation in the Programmable Analog resource." condition="`${deep_sleep &amp;&amp; aref_used &amp;&amp; (getExposedMember(&quot;pass[0]&quot;, &quot;deep_sleep_mode&quot;) ne &quot;CY_SYSANALOG_DEEPSLEEP_IPTAT_IZTAT_VREF&quot;)}`" paramId="deep_sleep" />
    -->    
  </DRCs>

  <ConfigFirmware>
      <ConfigInclude value="cy_ctdac.h" include="true" />
      <ConfigInclude value="cy_sysclk.h" include="true" />
      <ConfigInclude value="cyhal_hwmgr.h" include="true" guard="defined (CY_USING_HAL)" />

      <ConfigDefine name="`${INST_NAME}`_HW" value="CTDAC`${ctdac_instance}`" public="true" include="true" />

      <ConfigStruct name="`${INST_NAME . &quot;_config&quot;}`" type="cy_stc_ctdac_config_t" const="`${inFlash}`" public="true" include="true">
        <Member name="refSource" value="`${vref_source_is_vdda ? &quot;CY_CTDAC_REFSOURCE_VDDA&quot; : &quot;CY_CTDAC_REFSOURCE_EXTERNAL&quot;}`" />
        <Member name="formatMode" value="`${format_mode}`" />
        <Member name="updateMode" value="`${update_mode}`"/>
        <Member name="deglitchMode" value="`${output_is_unbuffered ? &quot;CY_CTDAC_DEGLITCHMODE_UNBUFFERED&quot; : &quot;CY_CTDAC_DEGLITCHMODE_BUFFERED&quot;}`"/>
        <Member name="outputMode" value="`${output_mode}`"/>
        <Member name="outputBuffer" value="`${output_is_unbuffered ? &quot;CY_CTDAC_OUTPUT_UNBUFFERED&quot; : &quot;CY_CTDAC_OUTPUT_BUFFERED&quot;}`"/>
        <Member name="deepSleep" value="`${deep_sleep ? &quot;CY_CTDAC_DEEPSLEEP_ENABLE&quot; : &quot;CY_CTDAC_DEEPSLEEP_DISABLE&quot;}`"/>
        <Member name="deglitchCycles" value="0"/>
        <Member name="value" value="`${initial_code}`"/>
        <Member name="nextValue" value="`${initial_code}`"/>
        <Member name="enableInterrupt" value="true"/>
        <Member name="configClock" value="false"/>
        <Member name="dividerType" value="CY_SYSCLK_DIV_8_BIT"/>
        <Member name="dividerNum" value="0"/>
        <Member name="dividerIntValue" value="0"/>
        <Member name="dividerFracValue" value="0"/>
      </ConfigStruct>

      <ConfigStruct name="`${INST_NAME}`_obj" type="cyhal_resource_inst_t" const="true" public="true" include="true" guard="defined (CY_USING_HAL)">
        <Member name="type" value="CYHAL_RSC_DAC" />
        <Member name="block_num" value="`${ctdac_instance}`U" />
        <Member name="channel_num" value="0U" />
      </ConfigStruct>
    
      <ConfigInstruction value="Cy_SysClk_PeriphAssignDivider(`${pclkDst}`, `${getExposedMember(pclk, &quot;clockSel&quot;)}`);" include="`${pclkOk}`" />
      <ConfigInstruction value="cyhal_hwmgr_reserve(&amp;`${INST_NAME}`_obj);" include="true" guard="defined (CY_USING_HAL)" />
  </ConfigFirmware>
</Personality>