<?xml version="1.0" encoding="utf-8"?>


<!--****************************************************************************
* \file udb_sdio.cypersonality
* \version 1.0
*
* \brief
* WICED Radio Interface personality description file.
*
********************************************************************************
* \copyright
* Copyright 2018-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
*     http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*****************************************************************************-->

<Personality id="mxs40udbsdio_p9" name="WICED Radio Interface Port 9" version="1.0" path="UDB" xmlns="http://cypress.com/xsd/cyhwpersonality_v1">
  <Dependencies>
    <IpBlock name="mxudb"/>
    <Resource name="udb" used="true"/>
  </Dependencies>
  <ExposedMembers/>
  <Parameters>
    <ParamDoc id="pdlDoc" name="Configuration Help" group="Peripheral Documentation" default="" linkText="Used only for the CYW9P62S1-43012EVB-01t" visible="true" desc="" />
    
    <ParamSignal port="clocks[0]" name="Clock" group="Inputs" visible="true" desc="The clock input that defines the operating frequency" canBeEmpty="false" />
    
    <ParamSignal port="in_p[240]" name="Data Line Input 0" group="Inputs" visible="true" desc="Data Line Input 0" canBeEmpty="false" isDependency="true"/>
    <ParamSignal port="in_p[241]" name="Data Line Input 1" group="Inputs" visible="true" desc="Data Line Input 1" canBeEmpty="false" isDependency="true"/>
    <ParamSignal port="in_p[242]" name="Data Line Input 2" group="Inputs" visible="true" desc="Data Line Input 2" canBeEmpty="false" isDependency="true"/>
    <ParamSignal port="in_p[243]" name="Data Line Input 3" group="Inputs" visible="true" desc="Data Line Input 3" canBeEmpty="false" isDependency="true"/>
    <ParamSignal port="in_p[244]" name="Command Input" group="Inputs" visible="true" desc="Command Input" canBeEmpty="false" isDependency="true"/>
    
    <ParamSignal port="port_if[80]" name="Data Line Output 0" group="Outputs" visible="true" desc="Data Line Output 0" canBeEmpty="false" isDependency="true"/>
    <ParamSignal port="port_if[81]" name="Data Line Output 1" group="Outputs" visible="true" desc="Data Line Output 1" canBeEmpty="false" isDependency="true"/>
    <ParamSignal port="port_if[82]" name="Data Line Output 2" group="Outputs" visible="true" desc="Data Line Output 2" canBeEmpty="false" isDependency="true"/>
    <ParamSignal port="port_if[83]" name="Data Line Output 3" group="Outputs" visible="true" desc="Data Line Output 3" canBeEmpty="false" isDependency="true"/>
    
    <ParamSignal port="port_oe[80]" name="Data Line Output Enable 0" group="Outputs" visible="true" desc="Data Line Output Enable 0" canBeEmpty="false" isDependency="true"/>
    <ParamSignal port="port_oe[81]" name="Data Line Output Enable 1" group="Outputs" visible="true" desc="Data Line Output Enable 1" canBeEmpty="false" isDependency="true"/>
    <ParamSignal port="port_oe[82]" name="Data Line Output Enable 2" group="Outputs" visible="true" desc="Data Line Output Enable 2" canBeEmpty="false" isDependency="true"/>
    <ParamSignal port="port_oe[83]" name="Data Line Output Enable 3" group="Outputs" visible="true" desc="Data Line Output Enable 3" canBeEmpty="false" isDependency="true"/>
    <ParamSignal port="port_if[84]" name="Command Output" group="Outputs" visible="true" desc="Command Output" canBeEmpty="false" isDependency="true"/>
    <ParamSignal port="port_oe[84]" name="Command Output Enable" group="Outputs" visible="true" desc="Command Output Enable" canBeEmpty="false" isDependency="true"/>
    <ParamSignal port="port_if[85]" name="SD Clock" group="Outputs" visible="true" desc="SD true" canBeEmpty="false" isDependency="true"/>
    
    <ParamSignal port="out_p[116]" name="DMA Write" group="Outputs" visible="true" desc="DMA Write" canBeEmpty="true"/>
    <ParamSignal port="out_p[105]" name="DMA Read" group="Outputs" visible="true" desc="DMA Read" canBeEmpty="true"/>
    <ParamSignal port="out_p[121]" name="DMA Command Write" group="Outputs" visible="true" desc="DMA Command Write" canBeEmpty="true"/>
    <ParamSignal port="out_p[117]" name="DMA Command Read" group="Outputs" visible="true" desc="DMA Command Read" canBeEmpty="true"/>
    
    <ParamBool id="clkSlowEnabled" name="clkSlowEnabled" group="Internal" default="`${isBlockUsed(&quot;srss[0].clock[0].slowclk[0]&quot;)}`" visible="false" editable="false" desc="" />
    <ParamBool id="clkPeriEnabled" name="clkPeriEnabled" group="Internal" default="`${isBlockUsed(&quot;srss[0].clock[0].periclk[0]&quot;)}`" visible="false" editable="false" desc="" />
    <ParamString id="clkSlowFreq" name="clkSlowFreq" group="Internal" default="`${clkSlowEnabled ? getExposedMember(&quot;srss[0].clock[0].slowclk[0]&quot;, &quot;frequency&quot;) : 0}`" visible="false" editable="false" desc="" />
    <ParamString id="clkPeriFreq" name="clkPeriFreq" group="Internal" default="`${clkPeriEnabled ? getExposedMember(&quot;srss[0].clock[0].periclk[0]&quot;, &quot;frequency&quot;) : 0}`" visible="false" editable="false" desc="" />
  </Parameters>
  <DRCs>
    <DRC type="ERROR" text="CLK_SLOW must be enabled" condition="`${!clkSlowEnabled}`" >
      <FixIt action="ENABLE_BLOCK" target="srss[0].clock[0].slowclk[0]" value="" valid="true" />
    </DRC>
    <DRC type="ERROR" text="CLK_SLOW must run at the same frequency as CLK_PERI." condition="`${clkSlowEnabled &amp;&amp; clkPeriEnabled &amp;&amp; (clkSlowFreq ne clkPeriFreq)}`" />
  </DRCs>
  <ConfigFirmware>
    <ConfigInclude value="cy_sysclk.h" include="true" />
    <ConfigInclude value="cyhal_hwmgr.h" include="true" guard="defined (CY_USING_HAL)" />
    
    <ConfigStruct name="`${INST_NAME}`_obj" type="cyhal_resource_inst_t" const="true" public="true" include="true" guard="defined (CY_USING_HAL)">
      <Member name="type" value="CYHAL_RSC_UDB" />
      <Member name="block_num" value="0U" />
      <Member name="channel_num" value="0U" />
    </ConfigStruct>
    
    <ConfigInstruction value="Cy_SysClk_PeriphAssignDivider(PCLK_UDB_CLOCKS0, CY_SYSCLK_DIV_8_BIT, 0u);" include="true" />
    <!--<ConfigInstruction value="SDIO_Host_Config_UDBs();" include="true" />-->
    <ConfigInstruction value="cyhal_hwmgr_reserve(&amp;`${INST_NAME}`_obj);" include="true" guard="defined (CY_USING_HAL)" />
  </ConfigFirmware>
</Personality>