<?xml version="1.0" encoding="utf-8"?>


<!--****************************************************************************
* \file hfclk.cypersonality
* \version 1.1
*
* \brief
* CLK_HF personality description file.
*
********************************************************************************
* \copyright
* Copyright 2018-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
*     http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*****************************************************************************-->

<Personality id="mxs40hfclk" name="CLK_HF" version="1.1" path="Clocks/Fast" xmlns="http://cypress.com/xsd/cyhwpersonality_v1">
  <Dependencies>
    <IpBlock name="mxs40srss" />
    <Resource name="srss\.clock\.hfclk" used="true" />
  </Dependencies>
  <ExposedMembers>
    <ExposedMember key="frequency" paramId="frequency" />
    <ExposedMember key="accuracy"  paramId="accuracy" />
    <ExposedMember key="error"     paramId="error" />
  </ExposedMembers>
  <Parameters>
    <!-- PDL documentation -->
    <ParamDoc id="pdlDoc" name="Configuration Help" group="Peripheral Documentation" default="file:///`${cy_libs_path()}`/docs/pdl_api_reference_manual/html/group__group__sysclk__clk__hf.html" linkText="Open High-Frequency Clocks Documentation" visible="true" desc="Opens the Peripheral Driver Library Documentation" />
  
    <ParamRange id="clockInst" name="clockInst" group="Internal" default="`${getInstNumber(&quot;hfclk&quot;)}`" min="0" max="`${NUM_HFROOT-1}`" resolution="1" visible="false" editable="false" desc="" /> 
    <ParamChoice id="sourceClockNumber" name="Source Clock" group="General" default="0" visible="true" editable="true" desc="The clock source for CLK_HF`${clockInst}`">
      <Entry name="CLK_PATH0"  value="0"  visible="`${NUM_CLKPATH >= 1}`"/>
      <Entry name="CLK_PATH1"  value="1"  visible="`${NUM_CLKPATH >= 2}`"/>
      <Entry name="CLK_PATH2"  value="2"  visible="`${NUM_CLKPATH >= 3}`"/>
      <Entry name="CLK_PATH3"  value="3"  visible="`${NUM_CLKPATH >= 4}`"/>
      <Entry name="CLK_PATH4"  value="4"  visible="`${NUM_CLKPATH >= 5}`"/>
      <Entry name="CLK_PATH5"  value="5"  visible="`${NUM_CLKPATH >= 6}`"/>
      <Entry name="CLK_PATH6"  value="6"  visible="`${NUM_CLKPATH >= 7}`"/>
      <Entry name="CLK_PATH7"  value="7"  visible="`${NUM_CLKPATH >= 8}`"/>
      <Entry name="CLK_PATH8"  value="8"  visible="`${NUM_CLKPATH >= 9}`"/>
      <Entry name="CLK_PATH9"  value="9"  visible="`${NUM_CLKPATH >= 10}`"/>
      <Entry name="CLK_PATH10" value="10" visible="`${NUM_CLKPATH >= 11}`"/>
      <Entry name="CLK_PATH11" value="11" visible="`${NUM_CLKPATH >= 12}`"/>
      <Entry name="CLK_PATH12" value="12" visible="`${NUM_CLKPATH >= 13}`"/>
      <Entry name="CLK_PATH13" value="13" visible="`${NUM_CLKPATH >= 14}`"/>
      <Entry name="CLK_PATH14" value="14" visible="`${NUM_CLKPATH >= 15}`"/>
      <Entry name="CLK_PATH15" value="15" visible="`${NUM_CLKPATH >= 16}`"/>
    </ParamChoice>
    
    <!-- If the FLL/PLL are enabled, their output drive the corresponding clock path -->
    <ParamBool id="isFllUsed" name="Is FLL Used" group="Internal" default="`${(sourceClockNumber eq 0) &amp;&amp; isBlockUsed(&quot;srss[0].clock[0].fll[0]&quot;)}`" visible="false" editable="false" desc="" />

    <ParamBool id="isPllUsed" name="Is PLL Used" group="Internal" default="`${(sourceClockNumber &gt; 0) &amp;&amp; (sourceClockNumber &lt;= NUM_PLL) &amp;&amp; isBlockUsed(&quot;srss[0].clock[0].pll[&quot; . (sourceClockNumber-1) . &quot;]&quot;)}`" visible="false" editable="false" desc="" />

    <ParamString id="sourceClock" name="Source clock resource" group="Internal" default="`${isFllUsed ? &quot;fll[0]&quot; :
                                                                                            isPllUsed ? &quot;pll[&quot; . (sourceClockNumber-1) . &quot;]&quot; :
                                                                                                        &quot;pathmux[&quot; . sourceClockNumber . &quot;]&quot;}`" visible="false" editable="false" desc="" />

    <ParamString id="sourceClockRsc" name="Source Clock" group="Internal" default="srss[0].clock[0].`${sourceClock}`" visible="false" editable="false" desc="" />

    <!-- Set an error if the source clock is not enabled or contains an error -->
    <ParamBool id="srcNotUsed" name="Clock Source Enabled" group="Internal" default="`${!isBlockUsed(sourceClockRsc)}`" visible="false" editable="false" desc="" />
    <ParamBool id="error" name="Clock Error" group="Internal" default="`${srcNotUsed || getExposedMember(sourceClockRsc, &quot;error&quot;)}`" visible="false" editable="false" desc="" />
    <ParamRange id="sourceFreq" name="sourceFrequency" group="Internal" default="`${!error ? getExposedMember(sourceClockRsc, &quot;frequency&quot;) : 0}`" min="0" max="400000000" resolution="0.001" visible="false" editable="false" desc="" />
    <ParamString id="accuracy" name="accuracy" group="Internal" default="`${!error ? getExposedMember(sourceClockRsc, &quot;accuracy&quot;) : 0}`" visible="false" editable="false" desc="" />
    <ParamString id="sourceFrequencyInfo" name="Source Frequency" group="General" default="`${formatFrequency(sourceFreq,accuracy)}`" visible="true" editable="false" desc="Source clock frequency" />
    

    <ParamChoice id="divider" name="Divider" group="General" default="1" visible="true" editable="true" desc="The source clock frequency divider">
      <Entry name="1" value="1" visible="true"/>
      <Entry name="2" value="2" visible="true"/>
      <Entry name="4" value="4" visible="true"/>
      <Entry name="8" value="8" visible="true"/>
    </ParamChoice>
    <ParamRange id="frequency" name="Frequency" group="Internal" default="`${sourceFreq / divider}`" min="0" max="400000000" resolution="1" visible="false" editable="false" desc="" />
    <!-- If the frequency is less than one MHz, display its value in kHz -->
    <ParamString id="frequencyInfo" name="Frequency" group="General" default="`${formatFrequency(frequency,accuracy)}`" visible="true" editable="false" desc="The resulting CLK_HF`${clockInst}` output clock frequency" />    
    <ParamSignal port="root_clk[0]" name="Clock Output" group="General" visible="true" desc="A high-frequency clock output driving specific periperals" canBeEmpty="true" >
      <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" >
        <Parameter id="DriveModes" severity="DEFAULT" reason="">
          <Fixed value="CY_GPIO_DM_STRONG_IN_OFF" />
        </Parameter>
      </Constraint>
      <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" >
        <Parameter id="DriveModes" severity="WARNING" reason="">
          <Choice>
            <Option value="CY_GPIO_DM_STRONG_IN_OFF"/>
            <Option value="CY_GPIO_DM_STRONG"/>
            <Option value="CY_GPIO_DM_OD_DRIVESLOW_IN_OFF"/>
            <Option value="CY_GPIO_DM_OD_DRIVESHIGH_IN_OFF"/>
            <Option value="CY_GPIO_DM_OD_DRIVESLOW"/>
            <Option value="CY_GPIO_DM_OD_DRIVESHIGH"/>
            <Option value="CY_GPIO_DM_PULLUP_IN_OFF"/>
            <Option value="CY_GPIO_DM_PULLDOWN_IN_OFF"/>
            <Option value="CY_GPIO_DM_PULLUP_DOWN_IN_OFF"/>
            <Option value="CY_GPIO_DM_PULLUP"/>
            <Option value="CY_GPIO_DM_PULLDOWN"/>
            <Option value="CY_GPIO_DM_PULLUP_DOWN"/>
          </Choice>
        </Parameter>
      </Constraint>
      <!--Constraint type="REQUIRE" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" >
        <Parameter id="DriveModes" severity="ERROR" reason="">
          <Fixed value="CY_GPIO_DM_STRONG_IN_OFF" />
        </Parameter>
      </Constraint-->
      <Constraint type="ACCEPT" targetLocation=".*" valid="true" />
    </ParamSignal>
  </Parameters>
  <DRCs>
    <DRC type="ERROR" text="Source clock for CLK_HF`${clockInst}` is not enabled" condition="`${srcNotUsed}`" >
      <FixIt action="ENABLE_BLOCK" target="`${sourceClockRsc}`" value="" valid="true" />
    </DRC>
    <DRC type="ERROR" text="CLK_HF0 is slower than legal min 200 kHz." condition="`${!error &amp;&amp; ((clockInst == 0) &amp;&amp; (sourceFreq &lt; 200000))}`" />
    <DRC type="INFO" text="The top-level System Clocks must be enabled to generate the clock initialization code" condition="`${!isBlockUsed(&quot;srss[0].clock[0]&quot;) &amp;&amp; clockInst == 0}`" location="srss[0].clock[0]" >
      <FixIt action="ENABLE_BLOCK" target="srss[0].clock[0]" value="" valid="true" />
    </DRC>
    <!-- Generate a DRC from HFCLK0 that prevents IMO from being disabled -->
    <DRC type="ERROR" text="The IMO cannot be disabled." condition="`${(clockInst eq 0) &amp;&amp; !isBlockUsed(&quot;srss[0].clock[0].imo[0]&quot;)}`" location="srss[0].clock[0]">
      <FixIt action="ENABLE_BLOCK" target="srss[0].clock[0].imo[0]" value="" valid="true" />
    </DRC>
    <!--DRC type="ERROR" text="Only one connection between the clock system and GPIO pins is possible, either EXTCLK or CLK_HF4." condition="`${hasConnection(&quot;root_clk&quot;, 0) &amp;&amp; isBlockUsed(&quot;srss[0].clock[0].ext[0]&quot;)}`" /-->
  </DRCs>
  <ConfigFirmware>
    <ConfigInclude value="cy_sysclk.h" include="true" />
    <ConfigDefine name="CY_CFG_SYSCLK_CLKHF`${clockInst}`_ENABLED" public="false" value="1" include="true" />
    <ConfigDefine name="CY_CFG_SYSCLK_CLKHF`${clockInst}`_DIVIDER" public="false" value="CY_SYSCLK_CLKHF_`${divider == 1 ? &quot;NO_DIVIDE&quot; : ((&quot;DIVIDE_BY_&quot;) . divider)}`" include="true" />
    <ConfigDefine name="CY_CFG_SYSCLK_CLKHF`${clockInst}`" public="true" value="`${clockInst}`UL" include="true" />
    <ConfigDefine name="CY_CFG_SYSCLK_CLKHF`${clockInst}`_FREQ_MHZ" public="false" value="`${frequency / 1000000}`UL" include="true" />
    <ConfigDefine name="CY_CFG_SYSCLK_CLKHF`${clockInst}`_CLKPATH" public="false" value="CY_SYSCLK_CLKHF_IN_CLKPATH`${sourceClockNumber}`" include="true" />
    <ConfigDefine name="CY_CFG_SYSCLK_CLKHF`${clockInst}`_CLKPATH_NUM" public="true" value="`${sourceClockNumber}`UL" include="true" />
    <ConfigFunction signature="__STATIC_INLINE void Cy_SysClk_ClkHf`${clockInst}`Init()" body="    Cy_SysClk_ClkHfSetSource(`${clockInst}`U, CY_CFG_SYSCLK_CLKHF`${clockInst}`_CLKPATH);&#xA;    Cy_SysClk_ClkHfSetDivider(`${clockInst}`U, CY_SYSCLK_CLKHF_`${divider == 1 ? &quot;NO_DIVIDE&quot; : ((&quot;DIVIDE_BY_&quot;) . divider)}`);" public="false" include="`${clockInst eq 0}`" guard="((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE)))" />
    <ConfigFunction signature="__STATIC_INLINE void Cy_SysClk_ClkHf`${clockInst}`Init()" body="    Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF`${clockInst}`, CY_CFG_SYSCLK_CLKHF`${clockInst}`_CLKPATH);&#xA;    Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF`${clockInst}`, CY_SYSCLK_CLKHF_`${divider == 1 ? &quot;NO_DIVIDE&quot; : ((&quot;DIVIDE_BY_&quot;) . divider)}`);&#xA;    Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF`${clockInst}`);" public="false" include="`${clockInst gt 0}`" guard="((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE)))" />
  </ConfigFirmware>
</Personality>