<?xml version="1.0" encoding="utf-8"?>


<!--****************************************************************************
* \file pll.cypersonality
* \version 2.0
*
* \brief
* PLL personality description file.
*
********************************************************************************
* \copyright
* Copyright 2018-2020 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
*     http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*****************************************************************************-->

<Personality id="mxs40pll" name="PLL" version="2.0" path="Clocks/Fast" xmlns="http://cypress.com/xsd/cyhwpersonality_v1">
  <Dependencies>
    <IpBlock name="mxs40srss" />
    <Resource name="srss\.clock\.pll" used="true" />
  </Dependencies>
  <ExposedMembers>
    <ExposedMember key="frequency" paramId="frequencyDisplay" />
    <ExposedMember key="accuracy"  paramId="accuracy" />
    <ExposedMember key="error"     paramId="error" />
  </ExposedMembers>
  <Parameters>
    <!-- PDL documentation -->
    <ParamDoc id="pdlDoc" name="Configuration Help" group="Peripheral Documentation" default="file:///`${cy_libs_path()}`/docs/pdl_api_reference_manual/html/group__group__sysclk__pll.html" linkText="Open PLL Documentation" visible="true" desc="Opens the Peripheral Driver Library Documentation" />

    <!-- PLL source clock and max device frequency -->
    <ParamRange id="clockInst" name="PLL Instance" group="Internal" default="`${getInstNumber(&quot;pll&quot;)}`" min="0" max="`${NUM_PLL-1}`" resolution="1" visible="false" editable="false" desc="" />
    <ParamString id="sourceClockRsc" name="Source Clock" group="Internal" default="srss[0].clock[0].pathmux[`${clockInst+1}`]" visible="false" editable="false" desc="" />
    <ParamBool id="srcNotUsed" name="Clock Source Enabled" group="Internal" default="`${!isBlockUsed(sourceClockRsc)}`" visible="false" editable="false" desc="" />
    <ParamBool id="srcError" name="Source Error" group="Internal" default="`${srcNotUsed || getExposedMember(sourceClockRsc, &quot;error&quot;)}`" visible="false" editable="false" desc="" />
    <ParamRange id="sourceFrequencyActual" name="Source Frequency" group="Internal" default="`${srcError ? 0 : getExposedMember(sourceClockRsc, &quot;frequency&quot;)}`" min="0" max="100000000" resolution="1" visible="false" editable="false" desc="" />
    <ParamString id="accuracy" name="accuracy" group="Internal" default="`${!srcError ? getExposedMember(sourceClockRsc, &quot;accuracy&quot;) : 0}`" visible="false" editable="false" desc="" />
    
    <ParamString id="sourceFrequencyInfo" name="Source Frequency" group="General" default="`${formatFrequency(sourceFrequencyActual,accuracy)}`" visible="true" editable="false" desc="Source clock frequency" />
    <!-- For ULP mode, Fpll_max = 50 MHz -->
    <ParamBool id="usingUlp" name="usingUlp" group="Internal" default="`${isBlockUsed(&quot;srss[0].power[0]&quot;) &amp;&amp; getExposedMember(&quot;srss[0].power[0]&quot;, &quot;usingUlp&quot;)}`" visible="false" editable="false" desc="" />
    <ParamString id="maxFrequency" name="maxFrequency" group="Internal" default="`${getDeviceAttr(&quot;CPU_MAX_MHZ&quot;)}`" visible="false" editable="false" desc="The maximum device frequency" />

    <ParamBool id="lowFrequencyMode" name="Low Frequency Mode" group="General" default="false" visible="true" editable="true" desc="VCO frequency range selection" />
    <ParamChoice id="configuration" name="Configuration" group="General" default="auto" visible="true" editable="true" desc="Choose the automatic or manual PLL tuning">
      <Entry name="Automatic" value="auto"   visible="true"/>
      <Entry name="Manual"    value="manual" visible="true"/>
    </ParamChoice>
    <ParamBool id="manConfig" name="Manual PLL Configuration" group="Internal" default="`${configuration eq manual}`" visible="false" editable="false" desc="" />
    <ParamRange id="desiredFrequency" name="Desired Frequency (MHz)" group="General" default="`${maxFrequency &gt; 100 ? 100 : maxFrequency}`" min="`${lowFrequencyMode ? 10.625 : 12.5}`" max="`${maxFrequency}`" resolution="0.001" visible="`${!manConfig}`" editable="true" desc="" />
    <ParamChoice id="optimization" name="Optimization" group="General" default="MinPower" visible="`${!manConfig}`" editable="true" desc="The feedback tuning options">
      <Entry name="Min Power" value="MinPower" visible="true" />
      <Entry name="Min Jitter" value="MinJitter" visible="true" />
    </ParamChoice>
    
    <!-- Set an error if the source clock is not enabled, contains an error or the source frequency is outside the valid range -->
    <ParamBool id="sourceFrequencyOutRange" name="sourceFrequencyOutRange" group="Internal" default="`${(sourceFrequencyActual &lt; 4000000) || (sourceFrequencyActual &gt; 64000000)}`" visible="false" editable="false" desc="" />
    <ParamBool id="error" name="Clock Error" group="Internal" default="`${srcError || sourceFrequencyOutRange}`" visible="false" editable="false" desc="" />

    <!-- Source Frequency -->
    <ParamRange id="sourceFrequency" name="sourceFrequency" group="Internal" default="`${!sourceFrequencyOutRange ? sourceFrequencyActual : 4000000}`" min="4000000" max="64000000" resolution="1" visible="false" editable="false" desc="" />

    <ParamString id="callSolver" name="callSolver" group="Internal" default="`${runTcl(&quot;pll_solver-2.0.tcl&quot;, sourceFrequency / 1000000.0, desiredFrequency, lowFrequencyMode, optimization eq MinPower)}`" visible="false" editable="false" desc="PLL clock solver" />
    <ParamRange id="feedback" name="Feedback (22-`${lowFrequencyMode ? &quot;56&quot; : &quot;112&quot;}`)" group="General" default="`${getTclVar(&quot;feedbackDiv&quot;, callSolver)}`" min="22" max="`${lowFrequencyMode ? &quot;56&quot; : &quot;112&quot;}`" resolution="1"  visible="true" editable="`${manConfig}`" desc="The feedback clock divider" />
    <ParamRange id="reference" name="Reference (1-18)" group="General" default="`${getTclVar(&quot;referenceDiv&quot;, callSolver)}`" min="1" max="18" resolution="1"  visible="true" editable="`${manConfig}`" desc="The reference clock divider" />
    <ParamRange id="output" name="Output (2-16)" group="General" default="`${getTclVar(&quot;outputDiv&quot;, callSolver)}`" min="2" max="16" resolution="1"  visible="true" editable="`${manConfig}`" desc="The output clock divider" />
    <ParamRange id="frequency" name="Frequency" group="Internal" default="`${sourceFrequency * feedback / reference / output}`" min="10625000" max="150000000" resolution="1" visible="false" editable="false" desc="" />
    <ParamRange id="frequencyDisplay" name="Display Frequency" group="Internal" default="`${(sourceFrequencyActual eq 0) ? sourceFrequencyActual : frequency}`" min="0" max="150000000" resolution="1" visible="false" editable="false" desc="" />
    <ParamString id="frequencyInfo" name="Actual Frequency" group="General" default="`${formatFrequency(!error ? frequency : 0,accuracy)}`" visible="true" editable="false" desc="The calculated resulting PLL output frequency" />

    <!-- Manual DRC verify params -->
    <ParamRange id="pfdFreq" name="PFD Frequency" group="internal" default="`${sourceFrequency / reference / 1000000.0}`" min="0" max="10000" resolution="0.001" visible="false" editable="false" desc="" />
    <ParamRange id="vcoFreq" name="VCO Frequency" group="internal" default="`${pfdFreq * feedback}`" min="0" max="10000" resolution="0.001" visible="false" editable="false" desc="" />
    <ParamRange id="vcoMin" name="VCO Min" group="internal" default="`${lowFrequencyMode ? 170 : 200}`" min="170" max="200" resolution="1" visible="false" editable="false" desc="" />
    <ParamRange id="vcoMax" name="VCO Max" group="internal" default="`${lowFrequencyMode ? 200 : 400}`" min="200" max="400" resolution="1" visible="false" editable="false" desc="" />

  </Parameters>
  <DRCs>
    <DRC type="ERROR" text="Source clock for PLL is not enabled" condition="`${srcNotUsed &amp;&amp; !hasBlock(&quot;srss[0].clock[0].pll[1]&quot;)}`" >
      <FixIt action="ENABLE_BLOCK" target="`${sourceClockRsc}`" value="" valid="true" />
    </DRC>
    <DRC type="ERROR" text="Source clock for PLL`${clockInst}` is not enabled" condition="`${srcNotUsed &amp;&amp; hasBlock(&quot;srss[0].clock[0].pll[1]&quot;)}`" >
      <FixIt action="ENABLE_BLOCK" target="`${sourceClockRsc}`" value="" valid="true" />
    </DRC>
    <DRC type="ERROR" text="The desired PLL frequency `${desiredFrequency}` MHz is higher than the maximum operating frequency `${maxFrequency}` MHz of the device" condition="`${!usingUlp &amp;&amp; desiredFrequency &gt; maxFrequency}`" paramId="desiredFrequency" />
    <DRC type="ERROR" text="The desired PLL frequency `${desiredFrequency}` MHz exceeds the maximum of 50 MHz when the ULP mode is used" condition="`${usingUlp &amp;&amp; desiredFrequency &gt; 50}`" paramId="desiredFrequency" />
    <DRC type="ERROR" text="Source clock for PLL is outside the valid range of 4 MHz - 64 MHz" condition="`${!srcError &amp;&amp; sourceFrequencyOutRange}`" paramId="sourceFrequencyInfo"/>
    <!-- Manual mode DRCs -->
    <DRC type="ERROR" text="VCO frequency out of range. VCO frequency (sourceFrequency * Feedback / Reference) of `${vcoFreq}` MHz is outside valid range of `${vcoMin}` MHz - `${vcoMax}` MHz" condition="`${manConfig &amp;&amp; (vcoFreq &lt; vcoMin || vcoFreq &gt; vcoMax)}`" />
    <DRC type="ERROR" text="PFD reference frequency out of range. PFD reference frequency (sourceFrequency / Reference) of `${pfdFreq}` MHz is outside valid range of 4 MHz - 8 MHz" condition="`${manConfig &amp;&amp; (pfdFreq &lt; 4 || pfdFreq &gt; 8)}`" />
    
  </DRCs>
  <ConfigFirmware>
    <ConfigInclude value="cy_sysclk.h" include="true" />
    <ConfigDefine name="CY_CFG_SYSCLK_PLL`${clockInst}`_ENABLED" value="1" public="false" include="true" />
    <ConfigDefine name="CY_CFG_SYSCLK_PLL`${clockInst}`_FEEDBACK_DIV" value="`${feedback}`" public="false" include="true" />
    <ConfigDefine name="CY_CFG_SYSCLK_PLL`${clockInst}`_REFERENCE_DIV" value="`${reference}`" public="false" include="true" />
    <ConfigDefine name="CY_CFG_SYSCLK_PLL`${clockInst}`_OUTPUT_DIV" value="`${output}`" public="false" include="true" />
    <ConfigDefine name="CY_CFG_SYSCLK_PLL`${clockInst}`_LF_MODE" value="`${lowFrequencyMode}`" public="false" include="true" />
    <ConfigDefine name="CY_CFG_SYSCLK_PLL`${clockInst}`_OUTPUT_MODE" value="CY_SYSCLK_FLLPLL_OUTPUT_AUTO" public="false" include="true" />
    <ConfigDefine name="CY_CFG_SYSCLK_PLL`${clockInst}`_OUTPUT_FREQ" value="`${frequency}`" public="false" include="true" />
    <ConfigStruct name="`${INST_NAME . &quot;_pllConfig&quot;}`" type="cy_stc_pll_manual_config_t" const="true" public="false" include="true" guard="((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE)))">
      <Member name="feedbackDiv" value="`${feedback}`" />
      <Member name="referenceDiv" value="`${reference}`" />
      <Member name="outputDiv" value="`${output}`" />
      <Member name="lfMode" value="`${lowFrequencyMode}`" />
      <Member name="outputMode" value="CY_SYSCLK_FLLPLL_OUTPUT_AUTO" />
    </ConfigStruct>
    <ConfigFunction signature="__STATIC_INLINE void Cy_SysClk_Pll`${clockInst}`Init()" body="    if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllManualConfigure(`${clockInst + 1}`U, &amp;`${INST_NAME}`_pllConfig))&#xA;    {&#xA;        cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);&#xA;    }&#xA;    if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(`${clockInst + 1}`U, 10000u))&#xA;    {&#xA;        cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);&#xA;    }" public="false" include="true" guard="((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE)))" />
  </ConfigFirmware>
</Personality>