<?xml version="1.0" encoding="utf-8"?>


<!--****************************************************************************
* \file timerclk.cypersonality
* \version 1.0
*
* \brief
* CLK_TIMER personality description file.
*
********************************************************************************
* \copyright
* Copyright 2018-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
*     http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*****************************************************************************-->

<Personality id="mxs40timerclk" name="CLK_TIMER" version="1.0" path="Clocks/Fast" xmlns="http://cypress.com/xsd/cyhwpersonality_v1">
  <Dependencies>
    <IpBlock name="mxs40srss" />
    <Resource name="srss\.clock\.timerclk" used="true" />
  </Dependencies>
  <ExposedMembers>
    <ExposedMember key="frequency" paramId="frequency" />
    <ExposedMember key="accuracy"  paramId="accuracy" />
  </ExposedMembers>
  <Parameters>
    <!-- PDL documentation -->
    <ParamDoc id="pdlDoc" name="Configuration Help" group="Peripheral Documentation" default="file:///`${cy_libs_path()}`/docs/pdl_api_reference_manual/html/group__group__sysclk__clk__timer.html" linkText="Open Timer Clock Documentation" visible="true" desc="Opens the Peripheral Driver Library Documentation" />

    <ParamChoice id="sourceClock" name="Source Clock" group="General" default="imo" visible="true" editable="true" desc="The source clock for the CLK_TIMER">
      <Entry name="IMO" value="imo" visible="true"/>
      <Entry name="CLK_HF0" value="hfclk" visible="true"/>
    </ParamChoice>
    <ParamString id="sourceClockRsc" name="Source Clock Resource" group="Internal" default="`${&quot;srss[0].clock[0].&quot; . sourceClock . &quot;[0]&quot;}`" visible="false" editable="false" desc="" />
    <ParamBool  id="error" name="Clock Error" group="Internal" default="`${!isBlockUsed(sourceClockRsc)}`" visible="false" editable="false" desc="" />
    <ParamRange id="sourceFreq" name="sourceFrequency" group="Internal" default="`${!error ? getExposedMember(sourceClockRsc, &quot;frequency&quot;) : 0}`" min="0" max="400000000" resolution="1" visible="false" editable="false" desc="" />
    <ParamString id="accuracy" name="Accuracy" group="Internal" default="`${!error ? getExposedMember(sourceClockRsc, &quot;accuracy&quot;) : 0}`" visible="false" editable="false" desc="" />
    <ParamString id="sourceFrequencyInfo" name="Source Frequency" group="General" default="`${formatFrequency(sourceFreq,accuracy)}`" visible="true" editable="false" desc="Source clock frequency" />
    <ParamChoice id="hf0Div" name="CLK_HF0 Divider" group="General" default="1" visible="true" editable="`${sourceClock eq hfclk}`" desc="CLK_HF0 can be additionaly divided before it is connected to the timer divider. If CLK_HF0 frequency is less than 100 MHz and has approximately 50% duty cycle, then no division is required. Otherwise, select a divide ratio of 2, 4, or 8.">
      <Entry name="1" value="1" visible="true"/>
      <Entry name="2" value="2" visible="true"/>
      <Entry name="4" value="4" visible="true"/>
      <Entry name="8" value="8" visible="true"/>
    </ParamChoice>
    <!-- Set an error if the source clock is not enabled -->

    <ParamRange id="timerDivider" name="Timer Divider" group="General" default="1" min="1" max="256" resolution="1" visible="true" editable="true" desc="" />
    <ParamRange id="frequency" name="Frequency" group="Internal" default="`${sourceFreq / timerDivider / (sourceClock eq imo ? 1 : hf0Div)}`" min="0" max="400000000" resolution="1" visible="false" editable="false" desc="" />
    <!-- If the frequency is less than one MHz, display its value in kHz -->
    <ParamString id="frequencyInfo" name="Frequency" group="General" default="`${formatFrequency(frequency,accuracy)}`" visible="true" editable="false" desc="The resulting CLK_TIMER output clock frequency" />
  </Parameters>
  <DRCs>
    <DRC type="ERROR" text="Source clock for CLK_TIMER is not enabled" condition="`${error}`" >
      <FixIt action="ENABLE_BLOCK" target="`${sourceClockRsc}`" value="" valid="true" />
    </DRC>
  </DRCs>
  <ConfigFirmware>
    <ConfigInclude value="cy_sysclk.h" include="true" />
    <ConfigDefine name="CY_CFG_SYSCLK_CLKTIMER_ENABLED" value="1" public="false" include="true" />
    <ConfigDefine name="CY_CFG_SYSCLK_CLKTIMER_SOURCE" value="CY_SYSCLK_CLKTIMER_IN_`${sourceClock eq imo ? &quot;IMO&quot; : &quot;HF0&quot; . (hf0Div == 1 ? &quot;_NODIV&quot; : &quot;_DIV&quot; . hf0Div)}`" public="false" include="true" />
    <ConfigDefine name="CY_CFG_SYSCLK_CLKTIMER_DIVIDER" value="`${timerDivider-1}`U" public="false" include="true" />
    <ConfigFunction signature="__STATIC_INLINE void Cy_SysClk_ClkTimerInit()" body="    Cy_SysClk_ClkTimerDisable();&#xA;    Cy_SysClk_ClkTimerSetSource(CY_SYSCLK_CLKTIMER_IN_`${sourceClock eq imo ? &quot;IMO&quot; : &quot;HF0&quot; . (hf0Div == 1 ? &quot;_NODIV&quot; : &quot;_DIV&quot; . hf0Div)}`);&#xA;    Cy_SysClk_ClkTimerSetDivider(`${timerDivider-1}`U);&#xA;    Cy_SysClk_ClkTimerEnable();" public="false" include="true" guard="((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE)))" />
  </ConfigFirmware>
</Personality>