GitBucket
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rockchip: rk3399: dram: set all ddr frequency pll_postdiv values to 0
The phy pll needs to get 2X frequency to the DDR, so set the pll_postdiv to 0. Signed-off-by: Lin Huang <hl@rock-chips.com> Signed-off-by: Derek Basehore <dbasehore@chromium.org> |
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Xing Zheng
committed
on 24 Feb 2017
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| plat/rockchip/rk3399/drivers/dram/dfs.c |
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