Initialise CPU contexts from entry_point_info
Consolidate all BL3-1 CPU context initialization for cold boot, PSCI and SPDs into two functions: * The first uses entry_point_info to initialize the relevant cpu_context for first entry into a lower exception level on a CPU * The second populates the EL1 and EL2 system registers as needed from the cpu_context to ensure correct entry into the lower EL This patch alters the way that BL3-1 determines which exception level is used when first entering EL1 or EL2 during cold boot - this is now fully determined by the SPSR value in the entry_point_info for BL3-3, as set up by the platform code in BL2 (or otherwise provided to BL3-1). In the situation that EL1 (or svc mode) is selected for a processor that supports EL2, the context management code will now configure all essential EL2 register state to ensure correct execution of EL1. This allows the platform code to run non-secure EL1 payloads directly without requiring a small EL2 stub or OS loader. Change-Id: If9fbb2417e82d2226e47568203d5a369f39d3b0f
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bl1/aarch64/bl1_arch_setup.c |
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bl31/aarch64/bl31_arch_setup.c |
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bl31/aarch64/context.S |
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bl31/bl31_main.c |
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bl31/context_mgmt.c |
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include/bl31/context_mgmt.h |
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include/common/bl_common.h |
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include/lib/aarch64/arch.h |
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include/lib/aarch64/arch_helpers.h |
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services/spd/tspd/tspd_common.c |
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services/spd/tspd/tspd_main.c |
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services/std_svc/psci/psci_afflvl_off.c |
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services/std_svc/psci/psci_afflvl_on.c |
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services/std_svc/psci/psci_afflvl_suspend.c |
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services/std_svc/psci/psci_common.c |
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services/std_svc/psci/psci_private.h |
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services/std_svc/psci/psci_setup.c |
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