Optimize SMCCC_ARCH_WORKAROUND_1 on Cortex A57/A72/A73 and A75
This patch implements a fast path for this SMC call on affected PEs by
detecting and returning immediately after executing the workaround.

NOTE: The MMU disable/enable workaround now assumes that the MMU was
enabled on entry to EL3.  This is a valid assumption as the code turns
on the MMU after reset and leaves it on until the core powers off.

Change-Id: I13c336d06a52297620a9760fb2461b4d606a30b3
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
1 parent d9bd656 commit 1d6d47a82a9aafc17d084738f79dc0c8d40dff45
@Dimitris Papastamos Dimitris Papastamos authored on 8 Jan 2018
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lib/cpus/aarch64/workaround_cve_2017_5715_bpiall.S
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lib/cpus/aarch64/workaround_cve_2017_5715_mmu.S