rockchip: add support save/restore configuration for DDR during enter S3

Fork: 0

LuminaSensum / arm-trusted-firmware

Browse code rockchip: add support save/restore configuration for DDR during enter S3 This patch intend to support save the registers of the DDR controller and PHY before suspend, and restore them after resume. Change-Id: Ia10b476c0b837628ac0f365416a7118292753e96 Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Derek Basehore <dbasehore@chromium.org> Signed-off-by: Caesar Wang <wxt@rock-chips.com> WIP_v2.3-LS master v2.2-LS v2.4-LS v2.3-rc2 v2.3-rc1 v2.3-rc0 v2.3 v2.2-rc2 v2.2-rc1 v2.2-rc0 v2.2 v2.1-rc1 v2.1-rc0 v2.1 v2.0-rc0 v2.0 v1.6-rc1 v1.6-rc0 v1.6 v1.5-rc3 v1.5-rc2 v1.5-rc1 v1.5-rc0 v1.5 v1.4-rc0 v1.4
1 parent f9ba21b commit 2831bc3a5f5dd9cdd6f272044f9f916e68797ff1 Caesar Wang authored on 26 Oct 2016

Browse code

This patch intend to support save the registers of the DDR controller
and PHY before suspend, and restore them after resume.

Change-Id: Ia10b476c0b837628ac0f365416a7118292753e96
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Derek Basehore <dbasehore@chromium.org>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

WIP_v2.3-LS master v2.2-LS v2.4-LS v2.3-rc2 v2.3-rc1 v2.3-rc0 v2.3 v2.2-rc2 v2.2-rc1 v2.2-rc0 v2.2 v2.1-rc1 v2.1-rc0 v2.1 v2.0-rc0 v2.0 v1.6-rc1 v1.6-rc0 v1.6 v1.5-rc3 v1.5-rc2 v1.5-rc1 v1.5-rc0 v1.5 v1.4-rc0 v1.4

1 parent f9ba21b commit 2831bc3a5f5dd9cdd6f272044f9f916e68797ff1

Caesar Wang authored on 26 Oct 2016

Patch

Unified Split

Showing 4 changed files

Ignore Space Show notes View plat/rockchip/rk3399/drivers/dram/suspend.c 0 → 100644

Ignore Space Show notes View plat/rockchip/rk3399/drivers/dram/suspend.h 0 → 100644

Ignore Space Show notes View plat/rockchip/rk3399/drivers/soc/soc.h

Ignore Space Show notes View plat/rockchip/rk3399/platform.mk

Show line notes below