rockchip: fixes the clock select and divide register for rk3399

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LuminaSensum / arm-trusted-firmware

Browse code rockchip: fixes the clock select and divide register for rk3399 As the new RK3399TRM v1.1, there are some wrong set for CRU_CLKSEL_CON register. As the CRU_CLKSEL_CON96～107 high 16-bit isn't write mask and the CRU_CLKSEL_CON offset is 0x100,not 0x80. Change-Id: Ie127e9de74b87100af9a0150aad43e89e4972529 WIP_v2.3-LS master v2.2-LS v2.4-LS v2.3-rc2 v2.3-rc1 v2.3-rc0 v2.3 v2.2-rc2 v2.2-rc1 v2.2-rc0 v2.2 v2.1-rc1 v2.1-rc0 v2.1 v2.0-rc0 v2.0 v1.6-rc1 v1.6-rc0 v1.6 v1.5-rc3 v1.5-rc2 v1.5-rc1 v1.5-rc0 v1.5 v1.4-rc0 v1.4
1 parent bfd9251 commit 4d5d98c77c0c3276cf6b9f39e6efbf5eccf44d6c Caesar Wang authored on 27 Sep 2016

Browse code

As the new RK3399TRM v1.1, there are some wrong set for CRU_CLKSEL_CON
register.

As the CRU_CLKSEL_CON96～107 high 16-bit isn't write mask and the
CRU_CLKSEL_CON offset is 0x100,not 0x80.

Change-Id: Ie127e9de74b87100af9a0150aad43e89e4972529

WIP_v2.3-LS master v2.2-LS v2.4-LS v2.3-rc2 v2.3-rc1 v2.3-rc0 v2.3 v2.2-rc2 v2.2-rc1 v2.2-rc0 v2.2 v2.1-rc1 v2.1-rc0 v2.1 v2.0-rc0 v2.0 v1.6-rc1 v1.6-rc0 v1.6 v1.5-rc3 v1.5-rc2 v1.5-rc1 v1.5-rc0 v1.5 v1.4-rc0 v1.4

1 parent bfd9251 commit 4d5d98c77c0c3276cf6b9f39e6efbf5eccf44d6c

Caesar Wang authored on 27 Sep 2016

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Ignore Space Show notes View plat/rockchip/rk3399/drivers/soc/soc.c

Ignore Space Show notes View plat/rockchip/rk3399/drivers/soc/soc.h

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