Workaround for Neoverse N1 erratum 1275112
Neoverse N1 erratum 1275112 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR_EL1 system register, which delays instruction fetch after branch misprediction. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: If7fe55fe92e656fa6aea12327ab297f2e6119833 Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> |
---|
|
docs/design/cpu-specific-build-macros.rst |
---|
lib/cpus/aarch64/neoverse_n1.S |
---|
lib/cpus/cpu-ops.mk |
---|