Add workaround for errata 1130799 for Cortex-A76
TLBI VAAE1 or TLBI VAALE1 targeting a page within hardware page
aggregated address translation data in the L2 TLB might cause
corruption of address translation data. Set bit 59 of CPUACTLR2_EL1 to
prevent this.

Change-Id: I59f3edea54e87d264e0794f5ca2a8c68a636e586
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
1 parent 9855159 commit 508d71108a06c7fce2eeef78659b9b7739cee6eb
@Louis Mayencourt Louis Mayencourt authored on 21 Feb 2019
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docs/cpu-specific-build-macros.rst
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lib/cpus/aarch64/cortex_a76.S
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lib/cpus/cpu-ops.mk