Add workaround for errata 790748 for Cortex-A75

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LuminaSensum / arm-trusted-firmware

Browse code Add workaround for errata 790748 for Cortex-A75 Internal timing conditions might cause the CPU to stop processing interrupts. Set bit 13 of CPUACTLR_EL1 to prevent this. Change-Id: Ifdd19dbcdb71bb0d9609cab1315c478aaedb03ba Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com> WIP_v2.3-LS master v2.2-LS v2.4-LS v2.3-rc2 v2.3-rc1 v2.3-rc0 v2.3 v2.2-rc2 v2.2-rc1 v2.2-rc0 v2.2 v2.1-rc1 v2.1-rc0 v2.1
1 parent 5f5d1ed commit 98551591f5371de2c2f0dee6be2e12b75653f04d Louis Mayencourt authored on 25 Feb 2019

Browse code

Internal timing conditions might cause the CPU to stop processing
interrupts. Set bit 13 of CPUACTLR_EL1 to prevent this.

Change-Id: Ifdd19dbcdb71bb0d9609cab1315c478aaedb03ba
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>

WIP_v2.3-LS master v2.2-LS v2.4-LS v2.3-rc2 v2.3-rc1 v2.3-rc0 v2.3 v2.2-rc2 v2.2-rc1 v2.2-rc0 v2.2 v2.1-rc1 v2.1-rc0 v2.1

1 parent 5f5d1ed commit 98551591f5371de2c2f0dee6be2e12b75653f04d

Louis Mayencourt authored on 25 Feb 2019

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