Add workaround for errata 1073348 for Cortex-A76

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LuminaSensum / arm-trusted-firmware

Browse code Add workaround for errata 1073348 for Cortex-A76 Concurrent instruction TLB miss and mispredicted return instruction might fetch wrong instruction stream. Set bit 6 of CPUACTLR_EL1 to prevent this. Change-Id: I2da4f30cd2df3f5e885dd3c4825c557492d1ac58 Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com> WIP_v2.3-LS master v2.2-LS v2.4-LS v2.3-rc2 v2.3-rc1 v2.3-rc0 v2.3 v2.2-rc2 v2.2-rc1 v2.2-rc0 v2.2 v2.1-rc1 v2.1-rc0 v2.1
1 parent 5cc8c7b commit 5c6aa01affe14c40efdebdc9450cdbc4ae0bc494 Louis Mayencourt authored on 25 Feb 2019

Browse code

Concurrent instruction TLB miss and mispredicted return instruction
might fetch wrong instruction stream. Set bit 6 of CPUACTLR_EL1 to
prevent this.

Change-Id: I2da4f30cd2df3f5e885dd3c4825c557492d1ac58
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>

WIP_v2.3-LS master v2.2-LS v2.4-LS v2.3-rc2 v2.3-rc1 v2.3-rc0 v2.3 v2.2-rc2 v2.2-rc1 v2.2-rc0 v2.2 v2.1-rc1 v2.1-rc0 v2.1

1 parent 5cc8c7b commit 5c6aa01affe14c40efdebdc9450cdbc4ae0bc494

Louis Mayencourt authored on 25 Feb 2019

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Ignore Space Show notes View docs/cpu-specific-build-macros.rst

Ignore Space Show notes View include/lib/cpus/aarch64/cortex_a76.h

Ignore Space Show notes View lib/cpus/aarch64/cortex_a76.S

Ignore Space Show notes View lib/cpus/cpu-ops.mk

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