Add workaround for errata 1220197 for Cortex-A76
Streaming store under specific conditions might cause deadlock or data
corruption. Set bit 25:24 of CPUECTLR_EL1, which disables write
streaming to the L2 to prevent this.

Change-Id: Ib5cabb997b35ada78b27e75787afd610ea606dcf
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
1 parent 508d711 commit 5cc8c7ba1b24ace2ef7345e96d933141f3609817
@Louis Mayencourt Louis Mayencourt authored on 25 Feb 2019
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docs/cpu-specific-build-macros.rst
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include/lib/cpus/aarch64/cortex_a76.h
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lib/cpus/aarch64/cortex_a76.S
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lib/cpus/cpu-ops.mk