Add workaround for errata 1220197 for Cortex-A76
Streaming store under specific conditions might cause deadlock or data corruption. Set bit 25:24 of CPUECTLR_EL1, which disables write streaming to the L2 to prevent this. Change-Id: Ib5cabb997b35ada78b27e75787afd610ea606dcf Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com> |
---|
|
docs/cpu-specific-build-macros.rst |
---|
include/lib/cpus/aarch64/cortex_a76.h |
---|
lib/cpus/aarch64/cortex_a76.S |
---|
lib/cpus/cpu-ops.mk |
---|