Add support for level specific cache maintenance operations
This patch adds level specific cache maintenance functions to cache_helpers.S. The new functions 'dcsw_op_levelx', where '1 <= x <= 3', allow to perform cache maintenance by set/way for that particular level of cache. With this patch, functions to support cache maintenance upto level 3 have been implemented since it is the highest cache level for most ARM SoCs. These functions are now utilized in CPU specific power down sequences to implement them as mandated by processor specific technical reference manual. Change-Id: Icd90ce6b51cff5a12863bcda01b93601417fd45c
WIP_v2.3-LS
master
v2.2-LS
v2.4-LS
v2.3-rc2
v2.3-rc1
v2.3-rc0
v2.3
v2.2-rc2
v2.2-rc1
v2.2-rc0
v2.2
v2.1-rc1
v2.1-rc0
v2.1
v2.0-rc0
v2.0
v1.6-rc1
v1.6-rc0
v1.6
v1.5-rc3
v1.5-rc2
v1.5-rc1
v1.5-rc0
v1.5
v1.4-rc0
v1.4
v1.3_rc2
v1.3_rc1
v1.3-rc0
v1.3
v1.2-rc0
v1.2
v1.1-rc3
v1.1-rc2
v1.1-rc1
v1.1-rc0
v1.1-Juno-0.1
v1.1
|
---|
|
lib/aarch64/cache_helpers.S |
---|
lib/cpus/aarch64/cortex_a53.S |
---|
lib/cpus/aarch64/cortex_a57.S |
---|