zynqmp: pm: Correct WDT clock database
WDT used by APU is FPD_WDT. FPD WDT clock is controlled by
FPD_SLCR.WDT_CLK_SEL register. Correct the same in WDT clock
database.

As per FPD_SLCR.WDT_CLK_SEL register, there can be only two
parents of WDT clock not three. Fix the same by correcting it's
parents in clock database.

Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Acked-by: Jolly Shah <jolly.shah@xilinx.com>
1 parent 6ad42b9 commit 96cd17f49d9a40ca3620b05d4e5cd09b8205f59a
@Siva Durga Prasad Paladugu Siva Durga Prasad Paladugu authored on 4 Sep 2018
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plat/xilinx/zynqmp/pm_service/pm_api_clock.c
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plat/xilinx/zynqmp/zynqmp_def.h