Tegra: Perform cache maintenance on video carveout memory
Currently, the non-overlapping video memory carveout region is cleared after
disabling the MMU at EL3. If at any exception level the carveout region is being
marked as cacheable, this zeroing of memory will not have an affect on the
cached lines. Hence, we first invalidate the dirty lines and update the memory
and invalidate again so that both caches and memory is zeroed out.

Change-Id: If3b2d139ab7227f6799c0911d59e079849dc86aa
1 parent 54dc71e commit e3616819a9802ae84e9ed23092e26968bc1f25ae
@Vikram Kanigiri Vikram Kanigiri authored on 10 Sep 2015
Achin Gupta committed on 14 Sep 2015
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plat/nvidia/tegra/common/drivers/memctrl/memctrl.c