Simplify management of SCTLR_EL3 and SCTLR_EL1
This patch reworks the manner in which the M,A, C, SA, I, WXN & EE bits of SCTLR_EL3 & SCTLR_EL1 are managed. The EE bit is cleared immediately after reset in EL3. The I, A and SA bits are set next in EL3 and immediately upon entry in S-EL1. These bits are no longer managed in the blX_arch_setup() functions. They do not have to be saved and restored either. The M, WXN and optionally the C bit are set in the enable_mmu_elX() function. This is done during both the warm and cold boot paths. Fixes ARM-software/tf-issues#226 Change-Id: Ie894d1a07b8697c116960d858cd138c50bc7a069
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bl1/aarch64/bl1_arch_setup.c |
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bl1/aarch64/bl1_entrypoint.S |
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bl2/aarch64/bl2_entrypoint.S |
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bl31/aarch64/bl31_arch_setup.c |
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bl31/aarch64/bl31_entrypoint.S |
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bl32/tsp/aarch64/tsp_entrypoint.S |
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include/lib/aarch64/arch.h |
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lib/aarch64/xlat_tables.c |
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services/std_svc/psci/psci_entry.S |
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