Workaround for CVE-2017-5715 on Cortex A57 and A72
Invalidate the Branch Target Buffer (BTB) on entry to EL3 by disabling
and enabling the MMU.  To achieve this without performing any branch
instruction, a per-cpu vbar is installed which executes the workaround
and then branches off to the corresponding vector entry in the main
vector table.  A side effect of this change is that the main vbar is
configured before any reset handling.  This is to allow the per-cpu
reset function to override the vbar setting.

This workaround is enabled by default on the affected CPUs.

Change-Id: I97788d38463a5840a410e3cea85ed297a1678265
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
1 parent 08e06be commit f62ad322695d16178db464dc062fe0af592c6780
@Dimitris Papastamos Dimitris Papastamos authored on 30 Nov 2017
Showing 8 changed files
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bl31/aarch64/runtime_exceptions.S
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bl31/bl31.mk
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docs/cpu-specific-build-macros.rst
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include/common/aarch64/el3_common_macros.S
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lib/cpus/aarch64/cortex_a57.S
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lib/cpus/aarch64/cortex_a72.S
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lib/cpus/aarch64/workaround_cve_2017_5715_mmu.S 0 → 100644
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lib/cpus/cpu-ops.mk