Merge pull request #1632 from Yann-lms/stm32mp1_mmc ...

Add MMC support for STM32MP1

Merge pull request #1582 from ldts/rcar_gen3/upstream ...

rcar_gen3: initial support

Merge pull request #1553 from glneo/dcache-late-disable ...

Allow D-Cache to remain on during core power-down

Merge pull request #1629 from robertovargas-arm/hw-assisted-coherency-lock ...

Optimize bakery locks when HW_ASSISTED_COHERENCY is enabled

Merge pull request #1631 from deepan02/deepak-arm/relocate-jump_if_cpu_midr ...

plat/arm: relocate the jump_if_cpu_midr macro.

Merge pull request #1628 from antonio-nino-diaz-arm/an/sharing ...

plat/arm: Small reorganization of platform code

rcar_gen3: drivers: watchdog ...

Signed-off-by: ldts <jramirez@baylibre.com>

rcar_gen3: drivers: serial controller interface ...

Signed-off-by: ldts <jramirez@baylibre.com>

rcar_gen3: drivers: spi multio bus controller ...

Signed-off-by: ldts <jramirez@baylibre.com>

rcar_gen3: drivers: rom api ...

Signed-off-by: ldts <jramirez@baylibre.com>

rcar_gen3: drivers: power controller ...

Signed-off-by: ldts <jramirez@baylibre.com>

rcar_gen3: drivers: console ...

Signed-off-by: ldts <jramirez@baylibre.com>

rcar_gen3: drivers: io [emmc/mem] ...

Signed-off-by: ldts <jramirez@baylibre.com>

rcar_gen3: drivers: i2c dvfs ...

Signed-off-by: ldts <jramirez@baylibre.com>

rcar_gen3: drivers: emmc ...

Signed-off-by: ldts <jramirez@baylibre.com>

rcar_gen3: drivers: dma ...

Signed-off-by: ldts <jramirez@baylibre.com>

rcar_gen3: drivers: micro delay generator ...

Signed-off-by: ldts <jramirez@baylibre.com>

rcar_gen3: drivers: cpld ...

Signed-off-by: ldts <jramirez@baylibre.com>

rcar_gen3: drivers: board identification ...

Signed-off-by: ldts <jramirez@baylibre.com>

rcar_gen3: drivers: avs [adaptive voltage scaling] ...

Signed-off-by: ldts <jramirez@baylibre.com>

rcar_gen3: drivers: authentication ...

Signed-off-by: ldts <jramirez@baylibre.com>

rcar_gen3: drivers: staging ...

- ddr
 - pfc [pin function controller]
 - qos [bandwidth]

checkpatch.pl is generating too many errors.

rcar-gen3: initial commit for the rcar-gen3 boards ...

Reference code:
==============

rar_gen3: IPL and Secure Monitor Rev1.0.22
https://github.com/renesas-rcar/arm-trusted-firmware [rcar_gen3]

Author: Takuya Sakata <takuya.sakata.wz@bp.renesas.com>
Date:   Thu Aug 30 21:26:41 2018 +0900
	Update IPL and Secure Monitor Rev1.0.22

General Information:
===================

This port has been tested on the Salvator-X Soc_id r8a7795 revision
ES1.1 (uses an SPD).

Build Tested:
-------------
ATFW_OPT="LSI=H3 RCAR_DRAM_SPLIT=1 RCAR_LOSSY_ENABLE=1"
MBEDTLS_DIR=$mbedtls

$ make clean bl2 bl31 rcar PLAT=rcar ${ATFW_OPT} SPD=opteed

Other dependencies:
------------------
* mbed_tls:
  git@github.com:ARMmbed/mbedtls.git [devel]

  Merge: 68dbc94 f34a4c1
  Author: Simon Butcher <simon.butcher@arm.com>
  Date:   Thu Aug 30 00:57:28 2018 +0100

* optee_os:
  https://github.com/BayLibre/optee_os

  Until it gets merged into OP-TEE, the port requires Renesas' Trusted
  Environment with a modification to support power management.

  Author: Jorge Ramirez-Ortiz <jramirez@baylibre.com>
  Date:   Thu Aug 30 16:49:49 2018 +0200
    plat-rcar: cpu-suspend: handle the power level
    Signed-off-by: Jorge Ramirez-Ortiz <jramirez@baylibre.com>

* u-boot:
  The port has beent tested using mainline uboot.

  Author: Fabio Estevam <festevam@gmail.com>
  Date:   Tue Sep 4 10:23:12 2018 -0300

*linux:
  The port has beent tested using mainline kernel.

  Author: Linus Torvalds <torvalds@linux-foundation.org>
  Date:   Sun Sep 16 11:52:37 2018 -0700
      Linux 4.19-rc4

Overview
---------

BOOTROM starts the cpu at EL3; In this port BL2 will therefore be entered
at this exception level (the Renesas' ATF reference tree [1] resets into
EL1 before entering BL2 - see its bl2.ld.S)

BL2 initializes DDR (and i2c to talk to the PMIC on some platforms)
before determining the boot reason (cold or warm).

During suspend all CPUs are switched off and the DDR is put in
backup mode (some kind of self-refresh mode). This means that BL2 is
always entered in a cold boot scenario.

Once BL2 boots, it determines the boot reason, writes it to shared
memory (BOOT_KIND_BASE) together with the BL31 parameters
(PARAMS_BASE) and jumps to BL31.

To all effects, BL31 is as if it is being entered in reset mode since
it still needs to initialize the rest of the cores; this is the reason
behind using direct shared memory access to  BOOT_KIND_BASE and
PARAMS_BASE instead of using registers to get to those locations (see
el3_common_macros.S and bl31_entrypoint.S for the RESET_TO_BL31 use
case).

Depending on the boot reason BL31 initializes the rest of the cores:
in case of suspend, it uses a MBOX memory region to recover the
program counters.

[1] https://github.com/renesas-rcar/arm-trusted-firmware
Tests
-----

* cpuidle
  -------
   enable kernel's cpuidle arm_idle driver and boot

* system suspend
  --------------
  $ cat suspend.sh
    #!/bin/bash
    i2cset -f -y 7 0x30 0x20 0x0F
    read -p "Switch off SW23 and press return " foo
    echo mem > /sys/power/state

* cpu hotplug:
  ------------
  $ cat offline.sh
    #!/bin/bash
    nbr=$1
    echo 0 > /sys/devices/system/cpu/cpu$nbr/online
    printf "ONLINE:  " && cat /sys/devices/system/cpu/online
    printf "OFFLINE: " && cat /sys/devices/system/cpu/offline

  $ cat online.sh
    #!/bin/bash
    nbr=$1
    echo 1 > /sys/devices/system/cpu/cpu$nbr/online
    printf "ONLINE:  " && cat /sys/devices/system/cpu/online
    printf "OFFLINE: " && cat /sys/devices/system/cpu/offline

Signed-off-by: ldts <jramirez@baylibre.com>

ti: k3: common: Do not disable cache on TI K3 core powerdown ...

Leave the caches on and explicitly flush any data that
may be stale when the core is powered down. This prevents
non-coherent interconnect access which has negative side-
effects on AM65x.

Signed-off-by: Andrew F. Davis <afd@ti.com>

scmi: Optimize bakery locks when HW_ASSISTED_COHERENCY is enabled ...

When HW_ASSISTED_COHERENCY is enabled we can use spinlocks
instead of using the more complex and slower bakery algorithm.

Change-Id: I9d791a70050d599241169b9160a67e57d5506564
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>

plat/arm: relocate the jump_if_cpu_midr macro. ...

macro jump_if_cpu_midr is used commonly by many arm platform.
It has now been relocated to common place to remove duplication
of code.

Change-Id: Ic0876097dbc085df4f90eadb4b7687dde7c726da
Signed-off-by: Deepak Pandey <Deepak.Pandey@arm.com>

stm32mp1: update platform files to use MMC devices ...

Signed-off-by: Yann Gautier <yann.gautier@st.com>

stm32mp1: add an IO to read MMC devices ...

Whereas the GPT table is read with io_block, the binaries to be loaded
(e.g. BL33) cannot use it, as it is not suitable to read them block by
block, or the boot time would be very bad.

Signed-off-by: Yann Gautier <yann.gautier@st.com>

stm32mp1: add an IO to read STM32IMAGE binaries ...

This IO is required to read binaries with STM32 header.
This header is added with the stm32image tool.

Signed-off-by: Yann Gautier <yann.gautier@st.com>

Add new defines for STM32MP1 platform ...

To boot on eMMC or SD-cards, STM32MP1 platform needs:
- GPT_IMAGE_ID to read GPT table on those devices
- STM32_IMAGE_ID and IO_TYPE_STM32IMAGE to read images with STM32 header
- IO_TYPE_MMC to have a IO for MMC devices

Signed-off-by: Yann Gautier <yann.gautier@st.com>