2019-03-12 |
plat: imx8m: Add the basic support for imx8mm
...
The i.MX8M Mini is new SOC of the i.MX8M family. it is
focused on delivering the latest and greatest video and
audio experience combining state-of-the-art media-specific
features with high-performance processing while optimized
for lowest power consumption. The i.MX 8M Mini Media Applications
Processor is 14nm FinFET product of the growing i.MX8M family
targeting the consumer & industrial market. It is built in 14LPP
to achieve both high performance and low power consumption
and relies on a powerful fully coherent core complex based on
a quad Cortex-A53 cluster with video and graphics accelerators
this patch add the basic support for i.MX8MM.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Jacky Bai
committed
on 12 Mar 2019
|
2019-03-01 |
Merge pull request #1751 from vwadekar/tegra-scatter-file-support
...
Tegra scatter file support
Antonio Niño Díaz
authored
on 1 Mar 2019
GitHub
committed
on 1 Mar 2019
|
2019-02-27 |
Tegra: Support for scatterfile for the BL31 image
...
This patch provides support for using the scatterfile format as
the linker script with the 'armlink' linker for Tegra platforms.
In order to enable the scatterfile usage the following changes
have been made:
* provide mapping for ld.S symbols in bl_common.h
* include bl_common.h from all the affected files
* update the makefile rules to use the scatterfile and armlink
to compile BL31
* update pubsub.h to add sections to the scatterfile
NOTE: THIS CHANGE HAS BEEN VERIFIED WITH TEGRA PLATFORMS ONLY.
Change-Id: I7bb78b991c97d74a842e5635c74cb0b18e0fce67
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Varun Wadekar
committed
on 27 Feb 2019
|
Merge pull request #1834 from thloh85-intel/s10_bl31
...
plat: intel: Add BL31 support to Intel Stratix10 SoCFPGA platform
Antonio Niño Díaz
authored
on 27 Feb 2019
GitHub
committed
on 27 Feb 2019
|
2019-02-25 |
plat: intel: Add BL31 support to Intel Stratix10 SoCFPGA platform
...
This adds BL31 support to Intel Stratix10 SoCFPGA platform. BL31 in TF-A
supports:
- PSCI calls to enable 4 CPU cores
- PSCI mailbox calls for FPGA reconfiguration
Signed-off-by: Loh Tien Hock <tien.hock.loh@intel.com>
Tien Hock, Loh
committed
on 25 Feb 2019
|
2019-02-22 |
Merge pull request #1836 from Yann-lms/docs_and_m4
...
Update documentation for STM32MP1 and add Cortex-M4 support
Antonio Niño Díaz
authored
on 22 Feb 2019
GitHub
committed
on 22 Feb 2019
|
2019-02-20 |
docs: stm32mp1: add links to documentation
...
A link to st.com page describing STM32MP1 is added.
Add the information about Cortex-M4 embedded in STM32MP1.
Correct typo for u-boot command.
Change-Id: Ie900f6ee59461c5e7ad8a8b06854abaf41fca3ce
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Yann Gautier
committed
on 20 Feb 2019
|
2019-02-19 |
Documentation for Versatile Express Fixed Virtual Platforms
...
This documentation contains information about the boot sequence,
code location and build procedure for fvp_ve platform.
Change-Id: I339903f663cc625cfabc75ed8e4accb8b2c3917c
Signed-off-by: Usama Arif <usama.arif@arm.com>
Usama Arif
committed
on 19 Feb 2019
|
2019-02-08 |
doc: Fix broken external links
...
Using Sphinx linkcheck on the TF-A docs revealed some broken
or permanently-redirected links. These have been updated where
possible.
Change-Id: Ie1fead47972ede3331973759b50ee466264bd2ee
Signed-off-by: Paul Beesley <paul.beesley@arm.com>
Paul Beesley
committed
on 8 Feb 2019
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2019-02-05 |
docs: add Tegra186 information to nvidia-tegra.rst
...
This patch adds information about the Tegra186 platforms to the
docs.
Change-Id: I69525c60a0126030dc15505ec7f02ccf8250be6f
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Varun Wadekar
committed
on 5 Feb 2019
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2019-01-23 |
Merge pull request #1768 from bryanodonoghue/integration+linaro_warp7-tbb
...
Integration+linaro warp7 tbb
Antonio Niño Díaz
authored
on 23 Jan 2019
GitHub
committed
on 23 Jan 2019
|
2019-01-18 |
Tegra: lib: library for profiling the cold boot path
...
The non secure world would like to profile the boot path for
the EL3 and S-EL1 firmwares. To allow it to do that, a non-secure
DRAM region (4K) is allocated and the base address is passed to
the EL3 firmware.
This patch adds a library to allow the platform code to store the
tag:timestamp pair to the shared memory. The tegra platform code
then uses the `record` method to add timestamps.
Original change by Akshay Sharan <asharan@nvidia.com>
Change-Id: Idbbef9c83ed84a508b04d85a6637775960dc94ba
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Varun Wadekar
committed
on 18 Jan 2019
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docs: warp7: Update WaRP7 description for TBB
...
This patch updates the WaRP7 build descriptions for booting WaRP7 in
Trusted Board Boot mode. TBB is the only mode we really intend to support
for this board so rather than maintain documentation for the old way of
doing it, this patch updates the description for TBB mode only.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Bryan O'Donoghue
committed
on 18 Jan 2019
|
2019-01-16 |
Tegra: support to set the L2 ECC and Parity enable bit
...
This patch adds capability to read the boot flag to enable L2 ECC
and Parity Protection bit for the Cortex-A57 CPUs. The previous
bootloader sets this flag value for the platform.
* with some coverity fix:
MISRA C-2012 Directive 4.6
MISRA C-2012 Rule 2.5
MISRA C-2012 Rule 10.3
MISRA C-2012 Rule 10.4
Change-Id: Id7303bbbdc290b52919356c31625847b8904b073
Signed-off-by: Harvey Hsieh <hhsieh@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Harvey Hsieh
authored
on 23 Nov 2016
Varun Wadekar
committed
on 16 Jan 2019
|
2018-12-04 |
plat: imx: Add i.MX8MQ basic support
...
i.MX8MQ is new SOC of NXP's i.MX8M family based on
A53. It can provide industry-leading audio, voice
and video processing for applications that scale
from consumer home audio to industrial building
automation and mobile computers
this patchset add the basic supoort to boot up
the 4 X A53. more feature will be added later.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Bai Ping
committed
on 4 Dec 2018
|
2018-11-20 |
rpi3: fix bad formatting in rpi3.rst
...
d4fd0219 (pull request #1685) introduced unwanted formatting
such as bold/italic in the description for RPI3_USE_UEFI_MAP.
Pete Batard
committed
on 20 Nov 2018
|
2018-11-19 |
rpi3: add RPI3_USE_UEFI_MAP build option
...
The default Raspberry Pi 3 memory mapping for ATF is geared towards
the use of uboot + Linux. This creates issues when trying to use
ATF with an UEFI payload and Windows on ARM64.
We therefore introduce new build option RPI3_USE_UEFI_MAP, that
enables the build process to use an alternate memory mapping that
is compatible with UEFI + Windows (as well as UEFI + Linux).
Fixes ARM-software/tf-issues#649
Signed-off-by: Pete Batard <pete@akeo.ie>
Pete Batard
committed
on 19 Nov 2018
|
2018-11-13 |
rpi3: add RPI3_RUNTIME_UART build option
...
Some OSes (e.g. Ubuntu 18.04 LTS on Raspberry Pi 3) may disable the
runtime UART in a manner that prevents the system from rebooting if
ATF tries to send runtime messages there.
Also, we don't want the firmware to share the UART with normal
world, as this can be a DoS attack vector into the secure world.
This patch fixes these 2 issues by introducing new build option
RPI3_RUNTIME_UART, that disables the runtime UART by default.
Fixes ARM-software/tf-issues#647
Signed-off-by: Pete Batard <pete@akeo.ie>
Pete Batard
committed
on 13 Nov 2018
|
2018-11-09 |
arm64: versal: Add support for new Xilinx Versal ACAPs
...
Xilinx is introducing Versal, an adaptive compute acceleration platform
(ACAP), built on 7nm FinFET process technology. Versal ACAPs combine Scalar
Processing Engines, Adaptable Hardware Engines, and Intelligent Engines with
leading-edge memory and interfacing technologies to deliver powerful
heterogeneous acceleration for any application. The Versal AI Core series has
five devices, offering 128 to 400 AI Engines. The series includes dual-core Arm
Cortex-A72 application processors, dual-core Arm Cortex-R5 real-time
processors, 256KB of on-chip memory with ECC, more than 1,900 DSP engines
optimized for high-precision floating point with low latency.
This patch adds Virtual QEMU platform support for
this SoC "versal_virt".
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Siva Durga Prasad Paladugu
committed
on 9 Nov 2018
|
2018-10-30 |
Merge pull request #1649 from Yann-lms/stm32mp1_doc_update
...
docs: stm32mp1: complete compilation and flashing steps
Antonio Niño Díaz
authored
on 30 Oct 2018
GitHub
committed
on 30 Oct 2018
|
2018-10-26 |
docs: gxbb: Add documentation
...
Change-Id: Ie2465c1ccc482bd8eb5e5a71c580543095e4ba94
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Antonio Nino Diaz
committed
on 26 Oct 2018
|
2018-10-24 |
rpi3: Add mem reserve region to DTB if present
...
When a device tree blob is present at a known address, instead of, for
example, relying on the user modifying the Linux command line to warn
about the memory reserved for the Trusted Firmware, pass it on the DTB.
The current code deletes the memory reserved for the default bootstrap
of the Raspberry Pi and adds the region used by the Trusted Firmware.
This system replaces the previous one consisting on adding
``memmap=16M$256M`` to the Linux command line. It's also meant to be
used by U-Boot and any other bootloader that understands DTB files.
Change-Id: I13ee528475fb043d6e8d9e9f24228e37ac3ac436
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Antonio Nino Diaz
committed
on 24 Oct 2018
|
docs: stm32mp1: complete compilation and flashing steps
...
Add U-Boot compilation information.
Add a chapter about how to populate SD-card.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Yann Gautier
committed
on 24 Oct 2018
|
2018-10-17 |
rcar-gen3: initial commit for the rcar-gen3 boards
...
Reference code:
==============
rar_gen3: IPL and Secure Monitor Rev1.0.22
https://github.com/renesas-rcar/arm-trusted-firmware [rcar_gen3]
Author: Takuya Sakata <takuya.sakata.wz@bp.renesas.com>
Date: Thu Aug 30 21:26:41 2018 +0900
Update IPL and Secure Monitor Rev1.0.22
General Information:
===================
This port has been tested on the Salvator-X Soc_id r8a7795 revision
ES1.1 (uses an SPD).
Build Tested:
-------------
ATFW_OPT="LSI=H3 RCAR_DRAM_SPLIT=1 RCAR_LOSSY_ENABLE=1"
MBEDTLS_DIR=$mbedtls
$ make clean bl2 bl31 rcar PLAT=rcar ${ATFW_OPT} SPD=opteed
Other dependencies:
------------------
* mbed_tls:
git@github.com:ARMmbed/mbedtls.git [devel]
Merge: 68dbc94 f34a4c1
Author: Simon Butcher <simon.butcher@arm.com>
Date: Thu Aug 30 00:57:28 2018 +0100
* optee_os:
https://github.com/BayLibre/optee_os
Until it gets merged into OP-TEE, the port requires Renesas' Trusted
Environment with a modification to support power management.
Author: Jorge Ramirez-Ortiz <jramirez@baylibre.com>
Date: Thu Aug 30 16:49:49 2018 +0200
plat-rcar: cpu-suspend: handle the power level
Signed-off-by: Jorge Ramirez-Ortiz <jramirez@baylibre.com>
* u-boot:
The port has beent tested using mainline uboot.
Author: Fabio Estevam <festevam@gmail.com>
Date: Tue Sep 4 10:23:12 2018 -0300
*linux:
The port has beent tested using mainline kernel.
Author: Linus Torvalds <torvalds@linux-foundation.org>
Date: Sun Sep 16 11:52:37 2018 -0700
Linux 4.19-rc4
Overview
---------
BOOTROM starts the cpu at EL3; In this port BL2 will therefore be entered
at this exception level (the Renesas' ATF reference tree [1] resets into
EL1 before entering BL2 - see its bl2.ld.S)
BL2 initializes DDR (and i2c to talk to the PMIC on some platforms)
before determining the boot reason (cold or warm).
During suspend all CPUs are switched off and the DDR is put in
backup mode (some kind of self-refresh mode). This means that BL2 is
always entered in a cold boot scenario.
Once BL2 boots, it determines the boot reason, writes it to shared
memory (BOOT_KIND_BASE) together with the BL31 parameters
(PARAMS_BASE) and jumps to BL31.
To all effects, BL31 is as if it is being entered in reset mode since
it still needs to initialize the rest of the cores; this is the reason
behind using direct shared memory access to BOOT_KIND_BASE and
PARAMS_BASE instead of using registers to get to those locations (see
el3_common_macros.S and bl31_entrypoint.S for the RESET_TO_BL31 use
case).
Depending on the boot reason BL31 initializes the rest of the cores:
in case of suspend, it uses a MBOX memory region to recover the
program counters.
[1] https://github.com/renesas-rcar/arm-trusted-firmware
Tests
-----
* cpuidle
-------
enable kernel's cpuidle arm_idle driver and boot
* system suspend
--------------
$ cat suspend.sh
#!/bin/bash
i2cset -f -y 7 0x30 0x20 0x0F
read -p "Switch off SW23 and press return " foo
echo mem > /sys/power/state
* cpu hotplug:
------------
$ cat offline.sh
#!/bin/bash
nbr=$1
echo 0 > /sys/devices/system/cpu/cpu$nbr/online
printf "ONLINE: " && cat /sys/devices/system/cpu/online
printf "OFFLINE: " && cat /sys/devices/system/cpu/offline
$ cat online.sh
#!/bin/bash
nbr=$1
echo 1 > /sys/devices/system/cpu/cpu$nbr/online
printf "ONLINE: " && cat /sys/devices/system/cpu/online
printf "OFFLINE: " && cat /sys/devices/system/cpu/offline
Signed-off-by: ldts <jramirez@baylibre.com>
Jorge Ramirez-Ortiz
authored
on 23 Sep 2018
ldts
committed
on 17 Oct 2018
|
2018-09-28 |
zynqmp: Migrate to new interfaces
...
- Remove references to removed build options.
- Migrate to bl31_early_platform_setup2().
Change-Id: Ibeb8982a0a841f55ce778c4f09f06b72b47b21d8
Tested-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Antonio Nino Diaz
committed
on 28 Sep 2018
|
2018-09-04 |
docs: warp7: Add description for the i.MX7 WaRP7 platform
...
This patch describes the boot-flow and building of the WaRP7 TF-A port.
What it describes is booting and unsigned TF-A.
A very brief section has been added on signing BL2 which is in no-way
comprehensive. For a comprehensive description of the signing process try
the Boundary Devices blog on the matter.
https://boundarydevices.com/high-assurance-boot-hab-dummies/
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Bryan O'Donoghue
committed
on 4 Sep 2018
|
2018-07-24 |
stm32mp1: Add platform documentation
...
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Yann Gautier
committed
on 24 Jul 2018
|
2018-07-16 |
rpi3: Move NS-DRAM out of the protected region
...
The Non-secure DRAM region shouldn't be protected in the range specified
in the Linux command line with memmap.
This change also increases the size of the Secure DRAM region.
Change-Id: I306e9e443a84b834c99739f54a534a3ca3be2424
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Antonio Nino Diaz
committed
on 16 Jul 2018
|
rpi3: Switch addresses of kernel and DTB
...
In the memory map of the documentation the kernel only had 16MiB of
allocated space. This leaves very little room for growth, so the
addresses of the DTB and the kernel have been interchanged.
The documentation has been updated to reflect this change.
Change-Id: Ib6eab69f047fa88561fb755397ce3a0b356c8860
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Antonio Nino Diaz
committed
on 16 Jul 2018
|
rpi3: Update documentation
...
Add information about direct Linux kernel boot for kernels that support
PSCI.
Change-Id: I05f76aa36398edabf411cb25a646437af1862e6e
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Antonio Nino Diaz
committed
on 16 Jul 2018
|