drivers: marvell: mg_conf_cm3: add basic driver ...

Implement function which will allow to start AP FW.

Change-Id: Ie0fc8ad138bf56b10809cdc92d1e5e96a2aaf33f
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>

tools: doimage: change the binary image alignment to 16 ...

Change the binary image alignment from 4 to 16.
The PKCS signature verification fails for unaligned images.

Change-Id: Ieb08dc3ea128790f542ad93e3c948117567a65af
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>

tools: doimage: migrate to mbedtls v2.8 APIs ...

Replace deprecated mbedtls_sha256 with mbedtls_sha256_ret
The mbedtls_pk_parse_key does not work correctly anymore
with the DER buffer embedded in the secure image extentson
using the buffer size as the the key length.
Move to mbedtls_pk_parse_subpubkey API that handles such
case correctly.
The DER format already contains the key length, so there
is no particular reason to supply it to the key parser.
Update the doimage version to 3.3

Change-Id: I0ec5ee84b7d1505b43138e0b7a6bdba44a6702b6
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>

Merge "plat/arm, dts: Update platform device tree for CoT" into integration

plat/arm, dts: Update platform device tree for CoT ...

Included cot_descriptors.dtsi in platform device tree
(fvp_tb_fw_config.dts).

Also, updated the maximum size of tb_fw_config to 0x1800
in order to accomodate the device tree for CoT descriptors.

Follow up patch will parse the device tree for these CoT descriptors
and fill the CoT descriptor structures at runtime instead of using
static CoT descriptor structures in the code base.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I90122bc713f6842b82fb019b04caf42629b4f45a

Merge "dts: Add CoT descriptor nodes and properties in device tree" into integration

dts: Add CoT descriptor nodes and properties in device tree ...

Added CoT descriptor nodes and properties in device tree.
Currently, CoT descriptors which are used by BL2 are added as part
of device tree.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: Iff23cff843e5489fac18bcee5f5d6a71de5ad0d0

Merge "make, doc: Add build option to create chain of trust at runtime" into integration

io_storage: remove redundant assigments ...

The assignments to 'result' are unneeded.

Change-Id: I18899f10bf9bd7f219f0e47a981683d8b4701bde
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

arm_fpga: Predefine DTB and BL33 load addresses ...

The memory layout for the FPGA is fairly uniform for most of the FPGA
images, and we already assume that DRAM starts at 2GB by default.

Prepopulate PRELOADED_BL33_BASE and FPGA_PRELOADED_DTB_BASE to some
sane default values, to simplify building some stock image.
If people want to deviate from that, they can always override those
addresses on the make command line.

Change-Id: I2238fafb3f8253a01ad2d88d45827c141d9b29dd
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

arm_fpga: Add Klein and Matterhorn support ...

To support FPGAs with those cores as well, as the respective cpulib
files to the Makefile.

Change-Id: I1a60867d5937be88b32b210c7817be4274554a76
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

arm_fpga: Support more CPU clusters ...

The maximum number of clusters is currently set to 2, which is quite
limiting. As there are FPGA images with 4 clusters, let's increase the
limit to 4.

Change-Id: I9a85ca07ebbd2a018ad9668536d867ad6b75e537
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

make, doc: Add build option to create chain of trust at runtime ...

Added a build option 'COT_DESC_IN_DTB' to create chain of trust
at runtime using fconf.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I92b257ac4ece8bbf56f05a41d1e4056e2422ab89

Merge "doc: Update CoT binding to make it more generic" into integration

doc: Update CoT binding to make it more generic ...

Updated the CoT binding document to show chain of trust relationship
with the help of 'authentication method' and 'authentication data'
instead of showing content of certificate and fixed rendering issue
while creating html page using this document.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: Ib48279cfe786d149ab69ddc711caa381a50f9e2b

drivers/stm32_hash: register resources as secure or not ...

Register in the shared resources driver the secure or non-secure state
of the HASH instances. Note that only BL32 needs to register the
shared peripheral because BL2 does not embed the shared resources
driver.

Change-Id: I7f78fa8e47da71d48ef8b1dfe4d6f040fe918d8b
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

drivers/stm32_gpio: register GPIO resources as secure or not ...

Register in the shared resources driver the secure or non-secure state
of the GPIO pins.

Change-Id: Ifda473bcbbb0af799be6587961d6641edf887605
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

drivers/stm32_iwdg: register IWDG resources as secure or not ...

Register in the shared resources driver the secure or non-secure state
of the IWDG instances.

Change-Id: I3a3bc9525447f6a2a465891ca3a3fd5fe664ca07
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

drivers/stm32mp_pmic: register PMIC resources as secure or not ...

Register in the shared resources driver the secure or non-secure
state of the PMIC.

Change-Id: Ic1f172ba62785018f8e9bb321782d725e2d2f434
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

stm32mp1: register shared resource per GPIO bank/pin ...

Introduce helper functions stm32mp_register_secure_gpio() and
stm32mp_register_non_secure_gpio() for drivers to register a
GPIO pin as secure or non-secure.

These functions are stubbed when shared resource driver is not
embedded in the BL image so that drivers do not bother whether they
shall register or not their resources.

Change-Id: I1fe98576c072ae31f75427c9ac5c9f6c4f1b6ed1
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

stm32mp1: register shared resource per IOMEM address ...

Introduce helper functions stm32mp_register_secure_periph_iomem()
and stm32mp_register_non_secure_periph_iomem() for drivers to
register a resource as secure or non-secure based on its SoC
interface registers base address.

These functions are stubbed when shared resources driver is not
embedded (!STM32MP_SHARED_RESOURCES) so that drivers embedded
in other BL stages do not bother whether they shall register or
not their resources.

Change-Id: Icebd05a930afc5964bc4677357da5d1b23666066
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

stm32mp1: allow non-secure access to reset upon periph registration ...

Update implementation of stm32mp_nsec_can_access_reset() based
on the registering of the shared resources.

Querying registering state locks further registration of
peripherals.

Change-Id: I5f38f2a3481780b9a71939d95984c4821c537aa4
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

stm32mp1: allow non-secure access to clocks upon periph registration ...

Update implementation of stm32mp_nsec_can_access_clock() based
on the registering of the shared resources.

Querying registering state locks further registration of peripherals.

Change-Id: If68f6d4a52c4742ba66244c6ea2d9afa08404137
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

stm32mp1: shared resources: peripheral registering ...

Define helper functions stm32mp_register_secure_periph() and
stm32mp_register_non_secure_periph() for platform drivers to
register a shared resource assigned to respectively secure
or non-secure world.

Some resources are related to clock resources. When a resource is
registered as secure, ensure its clock dependencies are also
registered as secure. Registering a non-secure resource does not
mandate its clock dependencies are also registered as non-secure.

Change-Id: I74975be8976b8d3bf18dcc807541a072803af6e3
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

drivers: st: clock: register parent of secure clocks ...

Introduce stm32mp1_register_clock_parents_secure() in stm32mp1
clock driver to allow platform shared resources to register as
secure the parent clocks of a clock registered as secure.

Change-Id: I53a9ab6aa78ee840ededce67e7b12a84e08ee843
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

stm32mp1: shared resources: add trace messages ...

Define from helper functions to get a human readable string
identifier from a shared resource enumerated ID. Use them to
make debug traces more friendly peripheral registering functions.

Change-Id: I9e207b8ce1d1e9250e242ca7e15461b9a1532f40
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

Merge "Upgrade libfdt source files" into integration

Merge "drivers: arm: gicv3: auto-detect presence of GIC600-AE" into integration

drivers: arm: gicv3: auto-detect presence of GIC600-AE ...

This patch adds the IIDR value for GIC600-AE to the gicv3_is_gic600()
helper function. This helps platforms supporting this version of the
GIC600 interrupt controller to function with the generic GIC driver.

Verified with tftf-validation test suite

******************************* Summary *******************************
> Test suite 'Framework Validation'
                                                                Passed
> Test suite 'Timer framework Validation'
                                                                Passed
=================================
Tests Skipped : 0
Tests Passed  : 6
Tests Failed  : 0
Tests Crashed : 0
Total tests   : 6
=================================
NOTICE:  Exiting tests.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I518ae7b56f7f372e374e453287d76ca370fc3574

Merge "corstone700: splitting the platform support into FVP and FPGA" into integration