2017-03-31 |
Flush console where necessary
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Call console_flush() before execution either terminates or leaves an
exception level.
Fixes: ARM-software/tf-issues#123
Change-Id: I64eeb92effb039f76937ce89f877b68e355588e3
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Antonio Nino Diaz
committed
on 31 Mar 2017
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Add and use plat_crash_console_flush() API
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This API makes sure that all the characters sent to the crash console
are output before returning from it.
Porting guide updated.
Change-Id: I1785f970a40f6aacfbe592b6a911b1f249bb2735
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Antonio Nino Diaz
committed
on 31 Mar 2017
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Add console_core_flush() in upstream platforms
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It is needed to add placeholders for this function because, as this is
not a `plat_xxx()` function, there aren't weak definitions of it in any
file.
If `console_flush()` is used and there isn't an implementation of
`console_core_flush()` in any file, the compilation will fail.
Change-Id: I50eb56d085c4c9fbc85d40c343e86af6412f3020
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Antonio Nino Diaz
committed
on 31 Mar 2017
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Add console_flush() to console API
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This function ensures that console output is flushed, for example
before shutting down or use by another component
In line with other console APIs, console_flush() wraps
console_core_flush().
Also implement console_core_flush() for PL011.
Change-Id: I3db365065e4de04a454a5c2ce21be335a23a01e4
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Antonio Nino Diaz
committed
on 31 Mar 2017
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2017-03-29 |
Merge pull request #880 from Summer-ARM/sq/tcr-memory-attribution
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Add support to change xlat_tables to non-cacheable
davidcunado-arm
authored
on 29 Mar 2017
GitHub
committed
on 29 Mar 2017
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Merge pull request #870 from douglas-raillard-arm/dr/remove_asm_signed_test
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Replace ASM signed tests with unsigned
davidcunado-arm
authored
on 29 Mar 2017
GitHub
committed
on 29 Mar 2017
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2017-03-28 |
Merge pull request #879 from Summer-ARM/sq/mt-support
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ARM platforms: Add support for MT bit in MPIDR
davidcunado-arm
authored
on 28 Mar 2017
GitHub
committed
on 28 Mar 2017
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Merge pull request #878 from vwadekar/tegra-memctrlv2-coverity-fix
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Tegra: memctrl_v2: fix logic to calculate TZRAM_ADDR_HI bits
davidcunado-arm
authored
on 28 Mar 2017
GitHub
committed
on 28 Mar 2017
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Add support to change xlat_tables to non-cacheable
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This patch adds an additional flag `XLAT_TABLE_NC` which marks the
translation tables as Non-cacheable for MMU accesses.
Change-Id: I7c28ab87f0ce67da237fadc3627beb6792860fd4
Signed-off-by: Summer Qin <summer.qin@arm.com>
Summer Qin
committed
on 28 Mar 2017
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2017-03-27 |
Tegra: memctrl_v2: fix logic to calculate TZRAM_ADDR_HI bits
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This patch fixes the logic to calculate the higher bits for TZRAM's base/end
addresses.
Fixes coverity error "31853: Wrong operator used (CONSTANT_EXPRESSION_RESULT)"
Change-Id: Iff62ef18cba59cd41ad63a5c71664872728356a8
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Varun Wadekar
committed
on 27 Mar 2017
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ARM platforms: Add support for MT bit in MPIDR
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This patch modifies some of the functions in ARM platform layer to cater
for the case when multi-threading `MT` is set in MPIDR. A new build flag
`ARM_PLAT_MT` is added, and when enabled, the functions accessing MPIDR
now assume that the `MT` bit is set for the platform and access the bit
fields accordingly.
Also, a new API plat_arm_get_cpu_pe_count is added when `ARM_PLAT_MT` is
enabled, returning the PE count within the physical cpu corresponding to
`mpidr`.
Change-Id: I04ccf212ac3054a60882761f4087bae299af13cb
Signed-off-by: Summer Qin <summer.qin@arm.com>
Summer Qin
committed
on 27 Mar 2017
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Merge pull request #873 from dp-arm/dp/makefile-reorg
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Move plat/common source file definitions to generic Makefiles
davidcunado-arm
authored
on 27 Mar 2017
GitHub
committed
on 27 Mar 2017
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2017-03-24 |
Merge pull request #872 from dp-arm/dp/fix-typo
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firmware-design: Fix typo in ToC header flags specification
davidcunado-arm
authored
on 24 Mar 2017
GitHub
committed
on 24 Mar 2017
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2017-03-23 |
Merge pull request #865 from vwadekar/tegra186-platform-support-v1
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Tegra186 platform support v1
davidcunado-arm
authored
on 23 Mar 2017
GitHub
committed
on 23 Mar 2017
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2017-03-22 |
Tegra186: implement support for System Suspend
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This patch adds the chip level support for System Suspend entry
and exit. As part of the entry sequence we first query the MCE
firmware to check if it is safe to enter system suspend. Once
we get a green light, we save hardware block settings and enter
the power state. As expected, all the hardware settings are
restored once we exit the power state.
Change-Id: I6d192d7568d6a555eb10efdfd45f6d79c20f74ea
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Varun Wadekar
committed
on 22 Mar 2017
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Tegra186: memctrl_v2: restore video memory settings
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The memory controller loses its settings when the device enters system
suspend state.
This patch adds a handler to restore the Video Memory settings in the
memory controller, which would be called after exiting the system suspend
state.
Change-Id: I1ac12426d7290ac1452983d3c9e05fabbf3327fa
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Varun Wadekar
committed
on 22 Mar 2017
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Tegra186: smmu: driver for the smmu hardware block
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This patch adds a device driver for the SMMU hardware block on
Tegra186 SoCs. We use the generic ARM SMMU-500 IP block on
Tegra186. The driver only supports saving the SMMU settings
before entering system suspend. The MC driver and the NS world
clients take care of programming their own settings.
Change-Id: Iab5a90310ee10f6bc8745451ce50952ab3de7188
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Varun Wadekar
committed
on 22 Mar 2017
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2017-03-20 |
Tegra: replace ASM signed tests with unsigned
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Replace the occurrences of signed condition codes where it was
unnecessary by an unsigned test as the unsigned tests allow the full
range of unsigned values to be used without inverting the result with
some large operands.
This reverts commit ee2c909 .
Change-Id: Ibaa5e8dfae6ad65bada3cda5f683d181fee37e53
Acked-by: Varun Wadekar <vwadekar@nvidia.com>
Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>
Douglas Raillard
committed
on 20 Mar 2017
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Tegra186: implement quasi power off (SC8) state
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This patch adds support for the SC8 system power off state. This
state keeps the sensor subsystem powered ON while powering down
the remaining parts of the SoC. The CPUs and DRAM are powered down
as part of this state entry and perform a cold boot when exiting SC8.
Change-Id: Iba65c661a7fe077a0d696f114bab3b4595e19a0d
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Varun Wadekar
committed
on 20 Mar 2017
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Tegra186: disable DCO operations for PSCI_CPU_OFF
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This patch disables the DCO operations when we turn OFF a
CPU. DCO operations are still ON when a CPU enters a power
down suspend state.
Change-Id: I954a800209ffcc9ab43a77f04040608cbbbd9055
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Varun Wadekar
committed
on 20 Mar 2017
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Tegra186: register FIQ interrupt sources
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This patch registers all the FIQ interrupt sources during platform
setup. Currently we support AON and TOP watchdog timer interrupts.
Change-Id: Ibccd866f00d6b08b574f765538525f95b49c5549
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Varun Wadekar
committed
on 20 Mar 2017
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Tegra: memctrl_v2: set NO_OVERRIDE for APE clients
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For all APE clients (APER, APEW, APEDMAR, APEDMAW) set NO_OVERRIDE
for MC_SID_CFG as ACAST/ADAST will be setup with the required SIDs
ie. 0x7F & 0x1E.
Original change by Nitin Kumbhar <nkumbhar@nvidia.com>
Change-Id: Idec981b3537cc95dac6ec37cdaa38bc45b16d232
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Varun Wadekar
committed
on 20 Mar 2017
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Tegra: memctrl_v2: implement MC txn override WAR
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This patch sets the Memory Controller's TXN_OVERRIDE registers
for most write clients to CGID_ADR. This ensures ordering is maintained.
In some cases WAW ordering problems could occur. There are different
settings for Tegra version A01 v A02.
Original changes by Alex Waterman <alexw@nvidia.com>
Change-Id: I82ea02afa43a24250ed56985757b83e78e71178c
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Varun Wadekar
committed
on 20 Mar 2017
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Tegra: memctrl_v2: check GPU state before VPR programming
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The GPU is the real consumer of the video protected memory region
and it needs to be in reset to pick up the new region.
This patch checks if the GPU is in reset before we program the new
video protected memory region settings.
Change-Id: I44f553bfcf07b1975abad53b245954be966c8aeb
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Varun Wadekar
committed
on 20 Mar 2017
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Tegra: memctrl_v2: no SID override for SCE block
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This patch fixes the incorrect override settings for the SCE
hardware block.
Original change by Pekka Pessi <ppessi@nvidia.com>
Change-Id: I33db55d6004331988b52ca70157aab1409f4829f
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Varun Wadekar
committed
on 20 Mar 2017
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Tegra186: fix per-cpu wake times for CPU power states
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This patch fixes the logic used to calculate the CPU index for
storing the per-cpu wake times. We use the MIDR register to
calculate the CPU index now. This allows us to store values for
Denver/A57 CPUs properly.
Change-Id: I9df0377afd4b92bbdaea495c0df06a9780a99d09
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Varun Wadekar
committed
on 20 Mar 2017
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Tegra186: add Video memory carveout settings
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This patch supports the TEGRA_SIP_NEW_VIDEOMEM_REGION SiP call to
program new video memory carveout settings from the NS world.
Change-Id: If9ed818fe71e6cb7461f225090105a4d8883b7a2
Signed-off-by: Wayne Lin <wlin@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Varun Wadekar
committed
on 20 Mar 2017
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Tegra186: support for C6/C7 CPU_SUSPEND states
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This patch adds support for the C6 and C7 CPU_SUSPEND states. C6 is
an idle state while C7 is a powerdown state.
The MCE block takes care of the entry/exit to/from these core power
states and hence we call the corresponding MCE handler to process
these requests. The NS driver passes the tentative time that the
core is expected to stay in this state as part of the power_state
parameter, which we store in a per-cpu array and pass it to the
MCE block.
Change-Id: I152acb11ab93d91fb866da2129b1795843dfa39b
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Varun Wadekar
committed
on 20 Mar 2017
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Tegra: memctrl_v2: secure the on-chip TZSRAM memory
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This patch programs the Memory controller's control registers
to disable non-secure accesses to the TZRAM. In case these
registers are already programmed by the BL2/BL30, then the
driver just bails out.
Change-Id: Ia1416988050e3d067296373060c717a260499122
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Varun Wadekar
committed
on 20 Mar 2017
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Tegra186: support for the latest platform port handlers
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This patch adds support for the newer platform handler functions. Commit
I6db74b020b141048b6b8c03e1bef7ed8f72fd75b merges the upstream code which
has already moved all the upstream supported platforms over to these
handler functions.
Change-Id: I621eff038f3c0dc1b90793edcd4dd7c71b196045
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Varun Wadekar
committed
on 20 Mar 2017
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