2016-04-07 |
Merge pull request #575 from soby-mathew/sm/new_tzc_driver
...
Refactor the TZC driver and add DMC-500 driver
danh-arm
committed
on 7 Apr 2016
|
Merge pull request #572 from jcastillo-arm/jc/tbb_nvcounter
...
TBB NVcounter support
danh-arm
committed
on 7 Apr 2016
|
Merge pull request #563 from sbranden/tf_issue_380
...
Add support for %z in tf_print()
danh-arm
committed
on 7 Apr 2016
|
2016-04-06 |
Merge pull request #581 from rockchip-linux/rockchip-atf-20160405
...
Support for Rockchip's family SoCs
danh-arm
committed
on 6 Apr 2016
|
2016-04-04 |
Support for Rockchip's family SoCs
...
This patch adds to support the RK3368 and RK3399 SoCs.
RK3368/RK3399 is one of the Rockchip family SoCs, which is an
multi-cores ARM SoCs.
This patch adds support to boot the Trusted Firmware on RK3368/RK3399
SoCs, and adds support to boot secondary CPUs, enter/exit core
power states for all CPUs in the slow/fast clusters.
This is the initial version for rockchip SoCs.(RK3368/RK3399 and next SoCs)
* Support arm gicv2 & gicv3.
* Boot up multi-cores CPU.
* Add generic CPU helper functions.
* Support suspend/resume.
* Add system_off & system_reset implementation.
* Add delay timer platform implementation.
* Support the new porting interface for the PSCI implementation.
Change-Id: I704bb3532d65e8c70dbd99b512c5e6e440ea6f43
Signed-off-by: Tony Xie <tony.xie@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Shengfei xu <xsf@rock-chips.com>
Tony Xie
authored
on 15 Jan 2016
Caesar Wang
committed
on 4 Apr 2016
|
Merge pull request #580 from soby-mathew/sm/ret_type_plat_ns_ep
...
Modify return type of plat_get_ns_image_entrypoint()
danh-arm
committed
on 4 Apr 2016
|
2016-04-01 |
Modify return type of plat_get_ns_image_entrypoint()
...
This patch modifies the return type of the platform API
`plat_get_ns_image_entrypoint()` from `unsigned long` to
`uintptr_t` in accordance with the coding guidelines.
Change-Id: Icb4510ca98b706aa4d535fe27e203394184fb4ca
Soby Mathew
committed
on 1 Apr 2016
|
Merge pull request #577 from antonio-nino-diaz-arm/an/remove-xlat-helpers
...
Remove xlat_helpers.c
danh-arm
committed
on 1 Apr 2016
|
Merge pull request #576 from mtk09422/bl31-security
...
mt8173: Protect BL31 memory from non-secure access
danh-arm
committed
on 1 Apr 2016
|
mt8173: Protect BL31 memory from non-secure access
...
BL31 usually handles confidential stuff, its memory must not be
read/write accessible from non-secure world. This patch protects
the BL31 memory range from non-secure read/write access.
Change-Id: I442fb92b667bb2f9a62d471a90508b1ba4489911
Signed-off-by: Jimmy Huang <jimmy.huang@mediatek.com>
Jimmy Huang
authored
on 29 Mar 2016
Yidi Lin
committed
on 1 Apr 2016
|
2016-03-31 |
Add support to program a DMC-500 TZC on ARM platforms
...
This patch adds support to program TrustZone protection on ARM platforms that
implement a DMC-500. arm_dmc_500.c has been added which implements the
arm_dmc_tzc_setup() function. This function relies on constants related to TZC
programming that are exported by each platform to program TrustZone protection
using the DMC-500 TrustZone controller driver. This function should be called
from plat_arm_security_setup() which is implemented by each platform.
Change-Id: I5400bdee9e4b29155fd11296a40693d512312f29
Vikram Kanigiri
authored
on 29 Jan 2016
Soby Mathew
committed
on 31 Mar 2016
|
Add ARM CoreLink DMC-500 driver to program TrustZone protection
...
The ARM CoreLink DMC-500 Dynamic Memory Controller provides the
programmable address region control of a TrustZone Address Space
Controller. The access permissions can be defined for eight
separate address regions plus a background or default region.
This patch adds a DMC-500 driver to define address regions and
program their access permissions as per ARM 100131_0000_02_en
(r0p0) document.
Change-Id: I9d33120f9480d742bcf7937e4b876f9d40c727e6
Vikram Kanigiri
authored
on 29 Jan 2016
Soby Mathew
committed
on 31 Mar 2016
|
Migrate ARM standard platforms to the refactored TZC driver
...
This patch migrates ARM Standard platforms to the refactored TZC driver.
Change-Id: I2a2f60b645f73e14d8f416740c4551cec87cb1fb
Soby Mathew
committed
on 31 Mar 2016
|
Refactor the ARM CoreLink TZC-400 driver
...
TrustZone protection can be programmed by both memory and TrustZone
address space controllers like DMC-500 and TZC-400. These peripherals
share a similar programmer's view.
Furthermore, it is possible to have multiple instances of each type of
peripheral in a system resulting in multiple programmer's views.
For example, on the TZC-400 each of the 4 filter units can be enabled
or disabled for each region. There is a single set of registers to
program the region attributes. On the DMC-500, each filter unit has its
own programmer's view resulting in multiple sets of registers to program
the region attributes. The layout of the registers is almost the same
across all these variations.
Hence the existing driver in `tzc400\tzc400.c` is refactored into the
new driver in `tzc\tzc400.c`. The previous driver file is still maintained
for compatibility and it is now deprecated.
Change-Id: Ieabd0528e244582875bc7e65029a00517671216d
Vikram Kanigiri
authored
on 28 Jan 2016
Soby Mathew
committed
on 31 Mar 2016
|
Remove xlat_helpers.c
...
lib/aarch64/xlat_helpers.c defines helper functions to build
translation descriptors, but no common code or upstream platform
port uses them. As the rest of the xlat_tables code evolves, there
may be conflicts with these helpers, therefore this code should be
removed.
Change-Id: I9f5be99720f929264818af33db8dada785368711
Antonio Nino Diaz
committed
on 31 Mar 2016
|
TBB: add non-volatile counter support
...
This patch adds support for non-volatile counter authentication to
the Authentication Module. This method consists of matching the
counter values provided in the certificates with the ones stored
in the platform. If the value from the certificate is lower than
the platform, the boot process is aborted. This mechanism protects
the system against rollback.
The TBBR CoT has been updated to include this method as part of the
authentication process. Two counters are used: one for the trusted
world images and another for the non trusted world images.
** NEW PLATFORM APIs (mandatory when TBB is enabled) **
int plat_get_nv_ctr(void *cookie, unsigned int *nv_ctr);
This API returns the non-volatile counter value stored
in the platform. The cookie in the first argument may be
used to select the counter in case the platform provides
more than one (i.e. TBSA compliant platforms must provide
trusted and non-trusted counters). This cookie is specified
in the CoT.
int plat_set_nv_ctr(void *cookie, unsigned int nv_ctr);
This API sets a new counter value. The cookie may be
used to select the counter to be updated.
An implementation of these new APIs for ARM platforms is also
provided. The values are obtained from the Trusted Non-Volatile
Counters peripheral. The cookie is used to pass the extension OID.
This OID may be interpreted by the platform to know which counter
must return. On Juno, The trusted and non-trusted counter values
have been tied to 31 and 223, respectively, and cannot be modified.
** IMPORTANT **
THIS PATCH BREAKS THE BUILD WHEN TRUSTED_BOARD_BOOT IS ENABLED. THE
NEW PLATFORM APIs INTRODUCED IN THIS PATCH MUST BE IMPLEMENTED IN
ORDER TO SUCCESSFULLY BUILD TF.
Change-Id: Ic943b76b25f2a37f490eaaab6d87b4a8b3cbc89a
Juan Castillo
committed
on 31 Mar 2016
|
Merge pull request #570 from davwan01/bl31-in-dram
...
Add support to load BL31 in DRAM
danh-arm
committed
on 31 Mar 2016
|
Merge pull request #554 from ljerry/tf_issue_368_ter
...
Enable asynchronous abort exceptions during boot
danh-arm
committed
on 31 Mar 2016
|
2016-03-30 |
Add support to load BL31 in DRAM
...
This patch adds an option to the ARM common platforms to load BL31 in the
TZC secured DRAM instead of the default secure SRAM.
To enable this feature, set `ARM_BL31_IN_DRAM` to 1 in build options.
If TSP is present, then setting this option also sets the TSP location
to DRAM and ignores the `ARM_TSP_RAM_LOCATION` build flag.
To use this feature, BL2 platform code must map in the DRAM used by
BL31. The macro ARM_MAP_BL31_SEC_DRAM is provided for this purpose.
Currently, only the FVP BL2 platform code maps in this DRAM.
Change-Id: If5f7cc9deb569cfe68353a174d4caa48acd78d67
David Wang
committed
on 30 Mar 2016
|
Add ISR_EL1 to crash report
...
Bring ISR bits definition as a mnemonic for troublershooters as well.
Signed-off-by: Gerald Lejeune <gerald.lejeune@st.com>
Gerald Lejeune
committed
on 30 Mar 2016
|
Remove DAIF bits handling macros
...
These macros are unused and redundant with other CPU system registers
functions.
Moreover enable_serror() function implementation may not reach its purpose
because it does not handle the value of SCR_EL3.EA.
Signed-off-by: Gerald Lejeune <gerald.lejeune@st.com>
Gerald Lejeune
committed
on 30 Mar 2016
|
Enable asynchronous abort exceptions during boot
...
Asynchronous abort exceptions generated by the platform during cold boot are
not taken in EL3 unless SCR_EL3.EA is set.
Therefore EA bit is set along with RES1 bits in early BL1 and BL31 architecture
initialisation. Further write accesses to SCR_EL3 preserve these bits during
cold boot.
A build flag controls SCR_EL3.EA value to keep asynchronous abort exceptions
being trapped by EL3 after cold boot or not.
For further reference SError Interrupts are also known as asynchronous external
aborts.
On Cortex-A53 revisions below r0p2, asynchronous abort exceptions are taken in
EL3 whatever the SCR_EL3.EA value is.
Fixes arm-software/tf-issues#368
Signed-off-by: Gerald Lejeune <gerald.lejeune@st.com>
Gerald Lejeune
committed
on 30 Mar 2016
|
cert_create: add non-volatile counter support
...
This patch adds non-volatile counter support to the Certificate
Generation tool. The TBBR Chain of Trust definition in the tool
has been extended to include the counters as certificate extensions.
The counter values can be specified in the command line.
The following default counter values are specified in the build
system:
* Trusted FW Non-Volatile counter = 0
* Non-Trusted FW Non-Volatile counter = 0
These values can be overridden by the platform at build time.
Change-Id: I7ea10ee78d72748d181df4ee78a7169b3ef2720c
Juan Castillo
committed
on 30 Mar 2016
|
2016-03-29 |
Merge pull request #561 from antonio-nino-diaz-arm/an/bootwrapper
...
Enable preloaded BL33 alternative boot flow
danh-arm
committed
on 29 Mar 2016
|
Merge pull request #560 from sandrine-bailleux-arm/sb/restructure-doc
...
Simplify Firmware Design document
danh-arm
committed
on 29 Mar 2016
|
Merge pull request #559 from soby-mathew/sm/cpu_ops_verbose_log
...
Make cpu operations warning a VERBOSE print
danh-arm
committed
on 29 Mar 2016
|
2016-03-23 |
Add support for %z in tf_print()
...
Add support for %z format specific in tf_printf() to support
printing data of type size_t
Fixes ARM-software/tf-issues#380
Signed-off-by Scott Branden <scott.branden@broadcom.com>
Scott Branden
committed
on 23 Mar 2016
|
2016-03-22 |
Simplify Firmware Design document
...
The Firmware Design document is meant to provide a general overview
of the Trusted Firmware code. Although it is useful to provide some
guidance around the responsibilities of the platform layer, it should
not provide too much platform specific implementation details. Right
now, some sections are too tied to the implementation on ARM
platforms. This makes the Firmware Design document harder to digest.
This patch simplifies this aspect of the Firmware Design document.
The sections relating the platform initialisations performed by the
different BL stages have been simplified and the extra details about
the ARM platforms implementation have been moved to the Porting Guide
when appropriate.
This patch also provides various documentation fixes and additions
in the Firmware Design and Platform Porting Guide. In particular:
- Update list of SMCs supported by BL1.
- Remove MMU setup from architectural inits, as it is actually
performed by platform code.
- Similarly, move runtime services initialisation, BL2 image
initialization and BL33 execution out of the platform
initialisation paragraph.
- List SError interrupt unmasking as part of BL1 architectural
initialization.
- Mention Trusted Watchdog enabling in BL1 on ARM platforms.
- Fix order of steps in "BL2 image load and execution" section.
- Refresh section about GICv3/GICv2 drivers initialisation on
ARM platforms.
Change-Id: I32113c4ffdc26687042629cd8bbdbb34d91e3c14
Sandrine Bailleux
committed
on 22 Mar 2016
|
Make cpu operations warning a VERBOSE print
...
The assembler helper function `print_revision_warning` is used when a
CPU specific operation is enabled in the debug build (e.g. an errata
workaround) but doesn't apply to the executing CPU's revision/part number.
However, in some cases the system integrator may want a single binary to
support multiple platforms with different IP versions, only some of which
contain a specific erratum. In this case, the warning can be emitted very
frequently when CPUs are being powered on/off.
This patch modifies this warning print behaviour so that it is emitted only
when LOG_LEVEL >= LOG_LEVEL_VERBOSE. The `debug.h` header file now contains
guard macros so that it can be included in assembly code.
Change-Id: Ic6e7a07f128dcdb8498a5bfdae920a8feeea1345
Soby Mathew
committed
on 22 Mar 2016
|
2016-03-16 |
Merge pull request #552 from antonio-nino-diaz-arm/an/cache-dts
...
Add cache topology info to FVP DTBs
danh-arm
committed
on 16 Mar 2016
|